Information

CHnFVAL[3:0] = 0010
(binary value)
channel (n) input
after the synchronizer
5-bit counter
filter output
system clock divided by 4
Time
Figure 37-177. Channel input filter example
37.4.5 Output Compare mode
The Output Compare mode is selected when:
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSnB:MSnA = 0:1
In Output Compare mode, the FTM can generate timed pulses with programmable
position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared, or
toggled.
When a channel is initially configured to Toggle mode, the previous value of the channel
output is held until the first output compare event occurs.
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel
(n) match (FTM counter = CnV).
TOF bit
...
...
0
1 1 1
2
2
3 3
4 45 5
0 0
previous value
previous value
channel (n) output
counter
overflow
counter
overflow
counter
overflow
channel (n)
match
channel (n)
match
CNT
MOD = 0x0005
CnV = 0x0003
CHnF bit
Figure 37-178. Example of the Output Compare mode when the match toggles the
channel output
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
896
Preliminary
Freescale Semiconductor, Inc.
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