Information

Section number Title Page
8.3.3 Security Interactions with Debug.................................................................................................................198
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................201
9.1.1 References....................................................................................................................................................203
9.2 The Debug Port.............................................................................................................................................................203
9.2.1 JTAG-to-SWD change sequence.................................................................................................................204
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................204
9.3 Debug Port Pin Descriptions.........................................................................................................................................205
9.4 System TAP connection................................................................................................................................................205
9.4.1 IR Codes.......................................................................................................................................................205
9.5 JTAG status and control registers.................................................................................................................................206
9.5.1 MDM-AP Control Register..........................................................................................................................207
9.5.2 MDM-AP Status Register............................................................................................................................209
9.6 Debug Resets................................................................................................................................................................210
9.7 AHB-AP........................................................................................................................................................................211
9.8 ITM...............................................................................................................................................................................212
9.9 Core Trace Connectivity...............................................................................................................................................212
9.10 TPIU..............................................................................................................................................................................212
9.11 DWT.............................................................................................................................................................................212
9.12 Debug in Low Power Modes........................................................................................................................................213
9.12.1 Debug Module State in Low Power Modes.................................................................................................214
9.13 Debug & Security.........................................................................................................................................................214
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................215
10.2 Signal Multiplexing Integration....................................................................................................................................215
10.2.1 Port control and interrupt module features..................................................................................................216
10.2.2 PCRn reset values for port A.......................................................................................................................216
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
9
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