Information

Register
access
Flash memory
controller
Transfers
Peripheral bus
controller 0
Transfers
Flash memory
Crossbar switch
Figure 3-20. Flash memory controller configuration
Table 3-30. Reference links to related information
Topic Related module Reference
Full description Flash memory
controller
Flash memory controller
System memory map System memory map
Clocking Clock Distribution
Transfers Flash memory Flash memory
Transfers Crossbar switch Crossbar Switch
Register access Peripheral bridge Peripheral bridge
3.5.3 SRAM Configuration
This section summarizes how the module has been configured in the chip.
SRAM upper
Transfers
SRAM controller
Cortex-M4
core
Crossbar
switch
SRAM lower
Figure 3-21. SRAM configuration
Table 3-31. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking Clock Distribution
Transfers SRAM controller SRAM controller
ARM Cortex-M4 core ARM Cortex-M4 core
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
91
General Business Information