Information

3.5.3.1 SRAM sizes
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of
SRAM for the devices covered in this document is shown in the following table.
Device SRAM (KB)
MK20DX128VLL7 32
MK20DX256VLL7 64
MK20DX64VMC7 16
MK20DX128VMC7 32
MK20DX256VMC7 64
3.5.3.2 SRAM Arrays
The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and
SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1]
This is illustrated in the following figure.
Memories and memory interfaces
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
92
Preliminary
Freescale Semiconductor, Inc.
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