Information

system clock
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
Figure 37-222. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1),
(PWMSYNC = 0), and software trigger was used
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 37-223. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(REINIT = 1), (PWMSYNC = 0), and a hardware trigger was used
If (SYNCMODE = 0), (REINIT = 1), and (PWMSYNC = 1) then this synchronization is
made on the next enabled hardware trigger. The TRIGn bit is cleared according to
Hardware trigger.
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 37-224. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used
Chapter 37 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
927
General Business Information