Information

SRAM_U
0x2000_0000
SRAM size / 2
SRAM_L
0x1FFF_FFFF
SRAM size / 2
0x2000_0000 – SRAM_size/2
0x2000_0000 + SRAM_size/2 - 1
Figure 3-22. SRAM blocks memory map
For example, for a device containing 64 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_7FFF
3.5.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode.
In VLLS2 the 16 KB region of SRAM_U from 0x2000_0000 is powered.
In VLLS1 no SRAM is retained; however, the 32-byte register file is available.
3.5.3.4 SRAM accesses
The SRAM is split into two logical arrays that are 32-bits wide.
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
port.
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the
backdoor port.
The backdoor port makes the SRAM accessible to the non-core bus masters (such as
DMA).
The following figure illustrates the SRAM accesses within the device.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
93
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