Information

Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MDIS FRZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
PIT_MCR field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
MDIS
Module Disable
Disables the module clock. This field must be enabled before any other setup is done.
0 Clock for PIT timers is enabled.
1 Clock for PIT timers is disabled.
0
FRZ
Freeze
Allows the timers to be stopped when the device enters the Debug mode.
0 Timers continue to run in Debug mode.
1 Timers are stopped in Debug mode.
38.3.2 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TSV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_LDVALn field descriptions
Field Description
31–0
TSV
Timer Start Value
Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt and
load this register value again. Writing a new value to this register will not restart the timer; instead the
value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new
value, the timer must be disabled and enabled again.
Memory map/register description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
968
Preliminary
Freescale Semiconductor, Inc.
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