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38.3.3 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TVL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_CVALn field descriptions
Field Description
31–0
TVL
Current Timer Value
Represents the current timer value, if the timer is enabled.
NOTE: • If the timer is disabled, do not use this field as its value is unreliable.
• The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is
set.
38.3.4 Timer Control Register (PIT_TCTRLn)
These registers contain the control bits for each timer.
Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CHN TIE TEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TCTRLn field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
CHN
Chain Mode
When activated, Timer n-1 needs to expire before timer n can decrement by 1.
Timer 0 can not be changed.
Table continues on the next page...
Chapter 38 Periodic Interrupt Timer (PIT)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
969
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