Information

3.5.8 FlexBus Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
FlexBus
Transfers
Peripheral
bridge 0
Crossbar switch
Figure 3-28. FlexBus configuration
Table 3-36. Reference links to related information
Topic Related module Reference
Full description FlexBus FlexBus
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.5.8.1 FlexBus clocking
The system provides a dedicated clock source to the FlexBus module's external
CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See
Clock Distribution for more details.
3.5.8.2 FlexBus signal multiplexing
The multiplexing of the FlexBus address and data signals is controlled by the port control
module. However, the multiplexing of some of the FlexBus control signals are controlled
by the port control and FlexBus modules. The port control module registers control
whether the FlexBus or another module signals are available on the external pin, while
the FlexBus's CSPMCR register configures which FlexBus signals are available from the
module. The control signals are grouped as illustrated:
Memories and memory interfaces
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
98
Preliminary
Freescale Semiconductor, Inc.
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