Information

40.5.1 CMT_IRO — Infrared Output
This output signal is driven by the modulator output when MSC[MCGEN] and
OC[IROPEN] are set. The IRO signal starts a valid transmission with a delay, after
MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits.
Table 40-5 shows how to calculate this delay.
The following table describes conditions for the IRO signal to be active.
If Then
MSC[MCGEN] is cleared and OC[IROPEN] is set The signal is driven by OC[IROL] . This enables user software
to directly control the state of the IRO signal by writing to
OC[IROL] .
OC[IROPEN] is cleared The signal is disabled and is not driven by the CMT module.
Therefore, CMT can be configured as a modulo timer for
generating periodic interrupts without causing signal activity.
Table 40-5. CMT_IRO signal delay calculation
Condition Delay (bus clock cycles)
MSC[CMTDIV] = 0 PPS[PPSDIV] + 2
MSC[CMTDIV] > 0 (PPS[PPSDIV] *2) + 3
40.6 Memory map/register definition
The following registers control and monitor the CMT operation.
The address of a register is the sum of a base address and an address offset. The base
address is defined at the chip level. The address offset is defined at the module level.
CMT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_2000 CMT Carrier Generator High Data Register 1 (CMT_CGH1) 8 R/W Undefined 40.6.1/991
4006_2001 CMT Carrier Generator Low Data Register 1 (CMT_CGL1) 8 R/W Undefined 40.6.2/992
4006_2002 CMT Carrier Generator High Data Register 2 (CMT_CGH2) 8 R/W Undefined 40.6.3/992
4006_2003 CMT Carrier Generator Low Data Register 2 (CMT_CGL2) 8 R/W Undefined 40.6.4/993
4006_2004 CMT Output Control Register (CMT_OC) 8 R/W 00h 40.6.5/993
4006_2005 CMT Modulator Status and Control Register (CMT_MSC) 8 R/W 00h 40.6.6/994
4006_2006 CMT Modulator Data Register Mark High (CMT_CMD1) 8 R/W Undefined 40.6.7/996
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
990
Preliminary
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