Information

CMT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_2007 CMT Modulator Data Register Mark Low (CMT_CMD2) 8 R/W Undefined 40.6.8/997
4006_2008 CMT Modulator Data Register Space High (CMT_CMD3) 8 R/W Undefined 40.6.9/997
4006_2009 CMT Modulator Data Register Space Low (CMT_CMD4) 8 R/W Undefined
40.6.10/
998
4006_200A CMT Primary Prescaler Register (CMT_PPS) 8 R/W 00h
40.6.11/
998
4006_200B CMT Direct Memory Access Register (CMT_DMA) 8 R/W 00h
40.6.12/
999
40.6.1 CMT Carrier Generator High Data Register 1 (CMT_CGH1)
This data register contains the primary high value for generating the carrier output.
Address: 4006_2000h base + 0h offset = 4006_2000h
Bit 7 6 5 4 3 2 1 0
Read
PH
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CGH1 field descriptions
Field Description
7–0
PH
Primary Carrier High Time Data Value
Contains the number of input clocks required to generate the carrier high time period. When
operating in Time mode, this register is always selected. When operating in FSK mode, this
register and the secondary register pair are alternately selected under the control of the
modulator. The primary carrier high time value is undefined out of reset. This register must
be written to nonzero values before the carrier generator is enabled to avoid spurious
results.
Chapter 40 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
991
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