Information

40.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1)
This data register contains the primary low value for generating the carrier output.
Address: 4006_2000h base + 1h offset = 4006_2001h
Bit 7 6 5 4 3 2 1 0
Read
PL
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CGL1 field descriptions
Field Description
7–0
PL
Primary Carrier Low Time Data Value
Contains the number of input clocks required to generate the carrier low time period. When
operating in Time mode, this register is always selected. When operating in FSK mode, this
register and the secondary register pair are alternately selected under the control of the
modulator. The primary carrier low time value is undefined out of reset. This register must be
written to nonzero values before the carrier generator is enabled to avoid spurious results.
40.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)
This data register contains the secondary high value for generating the carrier output.
Address: 4006_2000h base + 2h offset = 4006_2002h
Bit 7 6 5 4 3 2 1 0
Read
SH
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CGH2 field descriptions
Field Description
7–0
SH
Secondary Carrier High Time Data Value
Contains the number of input clocks required to generate the carrier high time period. When
operating in Time mode, this register is never selected. When operating in FSK mode, this
register and the primary register pair are alternately selected under control of the modulator.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
992
Preliminary
Freescale Semiconductor, Inc.
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