Information

CMT_OC field descriptions
Field Description
7
IROL
IRO Latch Control
Reads the state of the IRO latch. Writing to IROL changes the state of the IRO signal
when MSC[MCGEN] is cleared and IROPEN is set.
6
CMTPOL
CMT Output Polarity
Controls the polarity of the IRO signal.
0 The IRO signal is active-low.
1
The IRO signal is active-high.
5
IROPEN
IRO Pin Enable
Enables and disables the IRO signal. When the IRO signal is enabled, it is an output
that drives out either the CMT transmitter output or the state of IROL depending on
whether MSC[MCGEN] is set or not. Also, the state of output is either inverted or non-
inverted, depending on the state of CMTPOL. When the IRO signal is disabled, it is in
a high-impedance state and is unable to draw any current. This signal is disabled
during reset.
0 The IRO signal is disabled.
1
The IRO signal is enabled as output.
4–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
40.6.6 CMT Modulator Status and Control Register (CMT_MSC)
This register contains the modulator and carrier generator enable (MCGEN), end of cycle
interrupt enable (EOCIE), FSK mode select (FSK), baseband enable (BASE), extended
space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status bit.
Address: 4006_2000h base + 5h offset = 4006_2005h
Bit 7 6 5 4 3 2 1 0
Read EOCF
CMTDIV EXSPC BASE FSK EOCIE MCGEN
Write
Reset
0 0 0 0 0 0 0 0
CMT_MSC field descriptions
Field Description
7
EOCF
End Of Cycle Status Flag
Sets when:
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
994
Preliminary
Freescale Semiconductor, Inc.
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