Information

40.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)
The contents of this register are transferred to the space period register upon the
completion of a modulation period.
Address: 4006_2000h base + 9h offset = 4006_2009h
Bit 7 6 5 4 3 2 1 0
Read
SB[7:0]
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CMD4 field descriptions
Field Description
7–0
SB[7:0]
Controls the lower space periods of the modulator for all modes.
40.6.11 CMT Primary Prescaler Register (CMT_PPS)
This register is used to set the Primary Prescaler Divider field (PPSDIV).
Address: 4006_2000h base + Ah offset = 4006_200Ah
Bit 7 6 5 4 3 2 1 0
Read 0
PPSDIV
Write
Reset
0 0 0 0 0 0 0 0
CMT_PPS field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
PPSDIV
Primary Prescaler Divider
Divides the CMT clock to generate the Intermediate Frequency clock enable to the secondary prescaler.
0000 Bus clock ÷ 1
0001
Bus clock ÷ 2
0010
Bus clock ÷ 3
0011
Bus clock ÷ 4
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Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
998
Preliminary
Freescale Semiconductor, Inc.
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