Information
4.5.5.2 High-Speed Analog Comparator (CMP)
• Updated to allow the Analog input mux to be used as a pass through mux http://designpdm.freescale.net/Agile/object/
Change Request/TKT061929
• 6-bit DAC programmable reference generator output
• Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
• Comparator output supports:
• Sampled
• Windowed (ideal for certain PWM zero-crossing-detection applications
• Digitally filtered using external sample signal or scaled peripheral clock
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• Operational in all MCU power modes
4.5.5.3 12-Bit Digital-to-Analog Converter (DAC)
• Updated to allow a selectable VREFL option (VREF_OUT will be VREFL) http://designpdm.freescale.net/Agile/
object/Change Request/TKT062313
• 12-bit resolution
• Guaranteed 6-sigma monotocity over input word
• High- and low-speed conversions
• 1 μs conversion rate for high speed, 2 μs for low speed
• Power-down mode
• Choice of asynchronous or synchronous updates
• Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth
• Automatic mode allows programmable period, update rate, and range
• DMA support with configurable watermark level
4.5.5.4 Voltage Reference (VREF)
• Updated - Need 1.25V output and 2x option http://designpdm.freescale.net/Agile/object/Change Request/TKT061919
• Programmable trim register with 0.5mV steps, automatically loaded with room temp value upon reset
• Programmable mode selection:
• Off
• Bandgap out (or stabilization delay)
• Low-power buffer mode
• Tight-regulation buffer mode
• 1.25V output at room temperature
• Dedicated output pin
Timers
4.5.6.1 Programmable Delay Block (PDB)
• Up to 15 trigger input sources and software trigger source
• Up to eight configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC.
4.5.6
Timers
K20 Family Product Brief, Rev. 11, 08/2012
40 Freescale Semiconductor, Inc.