Information

• Idle line wakeup
• Address mark wakeup
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
• Support for CEA709.1-B protocol (LON) used in building automation and home networking systems
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
4.5.7.9 Secure Digital Host Controller (SDHC)
• Compatible with the following specifications:
• SD Host Controller Standard Specification, Version 2.0 (http://www.sdcard.org ) with test event register and
advanced DMA support
• MultiMediaCard System Specification, Version 4.2 (http://www.mmca.org )
• SD Memory Card Specification, Version 2.0 (http://www.sdcard.org ), supporting high capacity SD memory
cards
• SDIO Card Specification, Version 2.0 (http://www.sdcard.org )
• CE-ATA Card Specification, Version 1.0 (http://www.sdcard.org )
• Designed to work with CE-ATA, SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, and
RS-MMC cards
• SD bus clock frequency up to 50 MHz
• Supports 1-/4-bit SD and SDIO modes, 1-/4-/8-bit MMC modes, 1-/4-/8-bit CE-ATA devices
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC using 8 parallel data lines
• Single- and multi-block read and write
• 1-4096 byte block size
• Write-protection switch for write operations
• Synchronous and asynchronous abort
• Pause during the data transfer at a block gap
• SDIO read wait and suspend/resume operations
• Auto CMD12 for multi-block transfer
• Host can initiate non-data transfer commands while the data transfer is in progress
• Allows cards to interrupt the host in 1- and 4-bit SDIO modes
• Supports interrupt period, defined in the SDIO standard
• Fully configurable 128 x 32-bit FIFO for read/write data
• Internal DMA capabilities
• Supports voltage selection by configuring vendor specific register bit
• Supports advanced DMA to perform linked memory access
4.5.7.10 Synchronous Serial Interface (I
2
S)
• Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/
external clocks and frame syncs, operating in master or slave mode intended for audio support
• Master or slave mode operation
• Normal mode operation using frame sync
• Network mode operation allowing multiple devices to share the port with up to 32 time slots
• Programmable data interface modes, such as I
2
S, LSB aligned, and MSB aligned
• Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
• AC97 support
Communication interfaces
K20 Family Product Brief, Rev. 11, 08/2012
Freescale Semiconductor, Inc. 45