Information

Human-machine interface
4.5.8.1 General Purpose Input/Output (GPIO)
• Progammable glitch filter and interrupt with selectable polarity on all input pins
• Hysteresis and configurable pull up/down device on all input pins
• Configurable slew rate and drive strength on all output pins
• Independent pin value register to read logic level on digital pin
• Optional devices with 5V tolerance
4.5.8.2 Touch Sensor Input (TSI)
• 16 channel inputs, supporting up to 16 individual touch buttons
• 4 touch buttons can be combined for a slider
• Configurable button- and slider-sensitive interrupts
• Operation in low-power modes allows wakeup from lowest power mode via a single touch
• Option to use internal reference clock
5 Power modes
The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption
for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention,
partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The
following table compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes
(VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce
runtime power when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the
chip. The primary modes are augmented in a number of ways to provide lower power based on application needs.
Table 10. Chip power modes
Chip mode Description Core mode Normal
recovery
method
Normal run Allows maximum performance of chip. Default mode out of reset; on-
chip voltage regulator is on.
Run -
Normal Wait -
via WFI
Allows peripherals to function while the core is in sleep mode, reducing
power. NVIC remains sensitive to interrupts; peripherals continue to be
clocked.
Sleep Interrupt
Normal Stop -
via WFI
Places chip in static state. Lowest power mode that retains all registers
while maintaining LVD protection. NVIC is disabled; AWIC is used to
wake up from interrupt; peripheral clocks are stopped.
Sleep Deep Interrupt
Table continues on the next page...
4.5.8
Human-machine interface
K20 Family Product Brief, Rev. 11, 08/2012
46 Freescale Semiconductor, Inc.