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K20P81M100SF2

K20 Sub-Family Data Sheet

Supports the following:

MK20DX256ZVLK10,

MK20DN512ZVLK10,

MK20DX256ZVMB10,

MK20DN512ZVMB10

Features

•

Operating Characteristics

–

Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

•

Performance

– Up to 100 MHz ARM Cortex-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

•

Memories and memory interfaces

– Up to 512 KB program flash memory on non-

FlexMemory devices

– Up to 256 KB program flash memory on

FlexMemory devices

– Up to 256 KB FlexNVM on FlexMemory devices

– 4 KB FlexRAM on FlexMemory devices

– Up to 128 KB RAM

– Serial programming interface (EzPort)

– FlexBus external bus interface

•

Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

•

System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– 16-channel DMA controller, supporting up to 63

request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

•

Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– 128-bit unique identification (ID) number per chip

•

Human-machine interface

– Low-power hardware touch sensor interface (TSI)

– General-purpose input/output

•

Analog modules

– Two 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– 12-bit DAC

– Three analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

•

Timers

– Programmable delay block

– Eight-channel motor control/general purpose/PWM

timer

– Two 2-channel quadrature decoder/general purpose

timers

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

•

Communication interfaces

– USB full-/low-speed On-the-Go controller with on-

chip transceiver

– Two Controller Area Network (CAN) modules

– Two SPI modules

– Two I2C modules

– Four UART modules

– Secure Digital host controller (SDHC)

– I2S module

Freescale Semiconductor

Document Number: K20P81M100SF2

Data Sheet: Technical Data

Rev. 7, 02/2013

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (75 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: K20P81M100SF2 Rev. 7, 02/2013 K20P81M100SF2 K20 Sub-Family Data Sheet Supports the following: MK20DX256ZVLK10, MK20DN512ZVLK10, MK20DX256ZVMB10, MK20DN512ZVMB10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.
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Table of Contents 1 Ordering parts...........................................................................4 6 Peripheral operating requirements and behaviors....................23 1.1 Determining valid orderable parts......................................4 6.1 Core modules....................................................................23 2 Part identification......................................................................4 6.1.1 Debug trace timing specifications.......................
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9 Revision History........................................................................72 K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc.
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Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK20 and MK20 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
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Terminology and guidelines Field Description Values FFF Program flash memory size • • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK
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Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. Unit 1.1 V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min.
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Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 3.
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Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .
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Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.95 0.90 1.00 1.05 1.10 VDD (V) 3.
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Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.
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General Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) –25 25 mA ID VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.
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General 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.
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General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.
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General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Min. Typ.1 Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.
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General Table 4. Voltage and current operating behaviors (continued) Symbol IIND Description Min. Max. Unit Input leakage current, digital pins • VDD < VIN < 5.5 V ZIND Typ.1 Notes 4, 5 — 1 50 μA Input impedance examples, digital pins 4, 7 • VDD = 3.6 V — — 48 kΩ • VDD = 3.0 V — — 55 kΩ • VDD = 2.5 V — — 57 kΩ • VDD = 1.7 V — — 85 kΩ RPU Internal pullup resistors 20 35 50 kΩ 8 RPD Internal pulldown resistors 20 35 50 kΩ 9 1. 2. 3. 4. 5. 6. 7.
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General Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VDD slew rate ≥ 5.7 kV/s • VDD slew rate < 5.7 kV/s • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Unit Notes μs 1 — 300 — 1.7 V / (VDD slew rate) — 134 μs — 96 μs — 96 μs — 6.2 μs — 5.9 μs — 5.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — N/A — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — N/A — mA 8 IDD_STOP Stop mode current at 3.0 V • @ –40 to 25°C — 0.59 1.4 mA • @ 70°C — 2.26 7.9 mA • @ 105°C — 5.94 19.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when CPU is not accessing RTC registers Typ. Max. Unit Notes 10 • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C — 0.71 0.81 μA — 1.01 1.3 μA — 2.82 4.3 μA — 0.84 0.94 μA — 1.17 1.5 μA — 3.16 4.6 μA • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
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General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and 144MAPBGA packages Symbol Description Frequency band (MHz) 144LQFP 144MAPBGA Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.
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General 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8.
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General 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
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General 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 5.4.
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Peripheral operating requirements and behaviors 2. 3. 4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate.
PAGE 24
Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol J3 Description Min. Max. Unit • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.
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Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 7. Test Access Port timing K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 26 Freescale Semiconductor, Inc.
PAGE 27
Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 38.2 kHz — ± 0.3 ± 0.6 %fdco 1 Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 1.5 ± 4.
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Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol fdco Description DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit Notes 20 20.97 25 MHz 2, 3 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz — 180 — — 150 — — — 1 ms 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.
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Peripheral operating requirements and behaviors 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4.
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Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol RF RS Description Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors 6.3.3.2 Symbol fosc_lo tstart fec_extal32 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 Externally provided input clock frequency — 32.768 — kHz 2 700 — VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1.
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Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description teewr16bers Word-write to erased FlexRAM location execution time Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Symbol Description tnvmretd1k Data retention after up to 1 K cycles nnvmcycd Cycling endurance Min. Typ.1 Max.
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Peripheral operating requirements and behaviors • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.
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Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description Min. Max.
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Peripheral operating requirements and behaviors The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 25. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 11. FlexBus read timing diagram K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 40 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 29 and Table 30.
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Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2.
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Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Conditions1 Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Min. Typ.2 Max. Unit Notes • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.
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Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C Temp sensor voltage 25 °C 706 716 726 mV 1.
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Peripheral operating requirements and behaviors Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 29. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
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Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 — 450 Ksps 7 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.
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Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth PSRR Power supply rejection ratio CMRR Common mode rejection ratio Min. Typ.1 Max. • PGAG=0 0.95 1 1.05 • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.
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Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description ENOB Effective number of bits SINAD Signal-to-noise plus distortion ratio Min. Typ.1 Max. Unit Notes • Gain=1, Average=4 11.6 13.4 — bits • Gain=64, Average=4 7.2 9.6 — bits • Gain=1, Average=32 12.8 14.5 — bits 16-bit differential mode,fin=100Hz • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.
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Peripheral operating requirements and behaviors Table 31. Comparator and 6-bit DAC electrical specifications (continued) Symbol tDLS IDAC6b Description Min. Typ. Max. Unit Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1.
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Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 32. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.
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Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 33. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
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Peripheral operating requirements and behaviors Figure 18. Typical INL error vs. digital code K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 52 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors Figure 19. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 34. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference.
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Peripheral operating requirements and behaviors Table 35. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V Vout Voltage reference output — factory trim 1.1584 — 1.2376 V Vstep Voltage reference trim step — 0.
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Peripheral operating requirements and behaviors 6.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. 6.8.2 USB DCD electrical specifications Table 38. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.
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Peripheral operating requirements and behaviors Table 39. USB VREG electrical specifications (continued) Symbol ILIM Description Short circuit current Min. Typ.1 Max. Unit — 290 — mA Notes 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 6.8.4 CAN switching specifications See General switching specifications. 6.8.
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Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT DS6 First data Data Last data Figure 20. DSPI classic SPI timing — master mode Table 41. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.
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Peripheral operating requirements and behaviors 6.8.6 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
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Peripheral operating requirements and behaviors Table 43. Slave mode DSPI timing (full voltage range) (continued) Num Description Min. Max.
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Peripheral operating requirements and behaviors Table 44. I 2C timing (continued) Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum  Unit  ns Fall time of SDA and SCL signals tf — 300 20 +0.1Cb5 300 Set-up time for STOP condition tSU; STO 4 — 0.6 — µs Bus free time between STOP and START condition tBUF 4.7 — 1.3 — µs Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1.
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Peripheral operating requirements and behaviors 6.8.9 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 45. SDHC switching specifications Num Symbol Description Min. Max.
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Peripheral operating requirements and behaviors 6.8.10 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0).
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Peripheral operating requirements and behaviors Table 47. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors Table 49. I2S slave mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V 8 x tSYS — ns S11 I2S_BCLK cycle time (input) S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 10 — ns S14 I2S_FS input hold after I2S_BCLK 3.5 — ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 28.
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Dimensions 3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF. 4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF. 5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 8.
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Pinout NOTE The 81-pin ballmap assignments are currently being developed. The • in the entries in this package column indicate which signals are present on the package.
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Pinout 81 80 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K5 22 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 L4 23 XTAL32 XTAL32 XTAL32 L5 24 EXTAL32 EXTAL32 EXTAL32 K6 25 VBAT VBAT VBAT J6 26 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 b JTAG_TCLK/ SWD_CLK EZP_CLK H8 27 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI J7 28 PTA2 JTAG_
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Pinout 81 80 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 G8 46 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ b D10 47 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 C10 48 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 — 49 VSS VSS VSS — 50 VDD VDD VDD B10 51 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN E9 52 PTB17 TSI0_CH10 TSI0_CH10 PTB17
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Pinout 81 80 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort FB_BE31_24_ b D4 73 PTD0/ LLWU_P12 PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b D3 74 PTD1 PTD1 SPI0_SCK UART2_CTS_ b FB_CS0_b C3 75 PTD2/ LLWU_P13 PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FB_AD4 B3 76 PTD3 PTD3 SPI0_SIN UART2_TX FB_AD3 A3 77 PTD4/ LLWU_P14 PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ FTM0_CH4 b FB_AD2 EWM_IN A2 78 PTD5 ADC0_SE6b ADC0_SE6b PTD5 S
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Pinout 81 80 MAP LQFP BGA Pin Name Default ALT0 F8 — NC NC NC E8 — NC NC NC B6 — NC NC NC A6 — NC NC NC A5 — NC NC NC B5 — NC NC NC B4 — NC NC NC A4 — NC NC NC A10 — NC NC NC A9 — NC NC NC B1 — NC NC NC C2 — NC NC NC C1 — NC NC NC D2 — NC NC NC D1 — NC NC NC E1 — NC NC NC ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 8.2 K20 Pinouts The below figure shows the pinout diagram for the devices supported by this document.
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Pinout 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4 NC NC NC PTC8 PTC4 NC NC NC A B NC PTD6 PTD3 NC NC NC PTC7 PTC3 PTC0 PTB16 NC B C NC NC PTD2 PTC17 PTC11 PTC10 PTC6 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0 PTC16 PTC9 PTC5 PTC1 PTB18 PTB10 NC D E NC PTE2 PTE1 PTE0 VDD VDD VDD NC PTB17 NC NC E F USB0_DP USB0_DM NC PTE3 VDDA VSSA VSS NC NC NC NC F G VOUT33 VREGIN VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1 PTB0 G H
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PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC17 PTC16 VDD VSS PTC11 PTC10 PTC9 PTC8 PTC7 PTC6 PTC5 PTC4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Revision History PTB16 VOUT33 11 50 VDD VREGIN 12 49 VSS PGA0_DP/ADC0_DP0/ADC1_DP3 13 48 PTB11 PGA0_DM/ADC0_DM0/ADC1_DM3 14 47 PTB10 PGA1_DP/ADC1_DP0/ADC0_DP3 15 46 PTB3 PGA1_DM/ADC1_DM0/ADC0_DM3 16 45 PTB2 VDDA 17 44 PTB1 VREFH 18 43 PTB0 VREFL 19 42 RESET_b VSSA 20 41
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Revision History Table 51. Revision History (continued) Rev. No. Date 2 3/2011 Substantial Changes Many updates throughout Corrected 81- and 104-pin package codes 3 3/2011 Added sections that were inadvertently removed in previous revision 4 3/2011 Reworded IIC footnote in "Voltage and Current Operating Requirements" table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
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Revision History Table 51. Revision History (continued) Rev. No. Date 6 01/2012 Substantial Changes • • • • • • • • • • 7 02/2013 Added AC electrical specifications. Replaced TBDs with silicon data throughout. In "Power mode transition operating behaviors" table, removed entry times. Updated "EMC radiated emissions operating behaviors" to remove SAE level and also added data for 144LQFP. Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram". Added "ENOB vs.
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