Datasheet

Table 43. Slave mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit
DS9 DSPI_SCK input cycle time 8 x t
BUS
— ns
DS10 DSPI_SCK input high/low time (t
SCK
/2) - 4 (t
SCK/2)
+ 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
6.8.7 Inter-Integrated Circuit Interface (I
2
C) timing
Table 44. I
2
C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
0 100 0 400 kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
t
HD
; STA 4 — 0.6 — µs
LOW period of the SCL clock t
LOW
4.7 — 1.3 — µs
HIGH period of the SCL clock t
HIGH
4 — 0.6 — µs
Set-up time for a repeated START
condition
t
SU
; STA 4.7 — 0.6 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0
1
3.45
2
0
3
0.9
1
µs
Data set-up time t
SU
; DAT 250
4
— 100
2, 5
— ns
Rise time of SDA and SCL signals t
r
— 1000 20 +0.1C
b
6
300 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 59