Datasheet

81
MAP
BGA
80
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
K5 22 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L4 23 XTAL32 XTAL32 XTAL32
L5 24 EXTAL32 EXTAL32 EXTAL32
K6 25 VBAT VBAT VBAT
J6 26 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
H8 27 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 28 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
H9 29 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
J8 30 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 31 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_
BCLK
JTAG_TRST
E5 — VDD VDD VDD
G3 — VSS VSS VSS
K8 32 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_
PHA
L8 33 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
K9 34 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_
BCLK
L9 35 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD
J10 36 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b
I2S0_RX_FS
H10 37 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b
I2S0_MCLK I2S0_CLKIN
L10 38 VDD VDD VDD
K10 39 VSS VSS VSS
L11 40 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
K11 41 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1
J11 42 RESET_b RESET_b RESET_b
G11 43 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
G10 44 PTB1 ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
G9 45 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_
b
FTM0_FLT3
Pinout
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 67