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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 100 MHz I/O number 52

K20 Sub-Family Reference Manual

Supports: MK20DX256ZVLK10, MK20DN512ZVLK10,

MK20DX256ZVMB10, MK20DN512ZVMB10

Document Number: K20P81M100SF2RM

Rev. 6, Nov 2011

Summary of content (1619 pages)

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K20 Sub-Family Reference Manual Supports: MK20DX256ZVLK10, MK20DN512ZVLK10, MK20DX256ZVMB10, MK20DN512ZVMB10 Document Number: K20P81M100SF2RM Rev.
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K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 2 Freescale Semiconductor, Inc.
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Contents Section Number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................53 1.1.1 Purpose.........................................................................................................................................................53 1.1.2 Audience......................................................................
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Section Number 3.2 3.3 3.4 3.5 Title Page Core modules................................................................................................................................................................65 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................68 3.
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Section Number 3.6 Title Page 3.5.5 System Register File Configuration.............................................................................................................103 3.5.6 VBAT Register File Configuration..............................................................................................................104 3.5.7 EzPort Configuration...................................................................................................................................105 3.5.
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Section Number 3.7 3.8 3.9 3.10 Title Page Analog...........................................................................................................................................................................110 3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................110 3.7.2 CMP Configuration................................................................................................................
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Section Number 4.3 Title Page Flash Memory Map.......................................................................................................................................................155 4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................156 4.4 SRAM memory map................................................................................................................................................
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Section Number 5.7.11 Title Page TSI clocking.................................................................................................................................................178 Chapter 6 Reset and Boot 6.1 Introduction...................................................................................................................................................................181 6.2 Reset..............................................................................................
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Section Number Title Page Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................203 9.1.1 9.2 References....................................................................................................................................................205 The Debug Port..............................................................................................
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Section Number 10.2 10.3 10.4 Title Page Signal Multiplexing Integration....................................................................................................................................219 10.2.1 Port control and interrupt module features..................................................................................................220 10.2.2 Clock gating..............................................................................................................................
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Section Number 11.5 Title Page 11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................253 11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................253 Functional description...................................................................................................................................................254 11.5.
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Section Number 12.3 Title Page 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................286 12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................287 12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................288 12.2.
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Section Number Title Page 14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................318 14.4.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................320 Chapter 15 Low-leakage wake-up unit (LLWU) 15.1 Introduction........................................................................................................................................................
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Section Number 16.2 16.3 Title Page Memory Map/Register Descriptions.............................................................................................................................341 16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................342 16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................342 16.2.
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Section Number 18.3 18.4 Title Page Memory Map/Register Definition.................................................................................................................................365 18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................368 18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................370 18.3.
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Section Number Title Page Chapter 20 Direct memory access multiplexer (DMAMUX) 20.1 Introduction...................................................................................................................................................................403 20.1.1 Overview......................................................................................................................................................403 20.1.2 Features..........................................................
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Section Number Title Page 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................443 21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................444 21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................445 21.3.
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Section Number 21.3.31 Title Page TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)............................................................................................................469 21.4 21.5 Functional description...................................................................................................................................................470 21.4.1 eDMA basic data flow..................................................
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Section Number Title Page 22.4.3 EWM Counter..............................................................................................................................................498 22.4.4 EWM Compare Registers............................................................................................................................498 22.4.5 EWM Refresh Mechanism...........................................................................................................................
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Section Number 23.8 23.9 Title Page 23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................517 23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................517 23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................518 23.7.12 Watchdog Prescaler Register (WDOG_PRESC)...........................
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Section Number 24.5 Title Page 24.4.3 MCG Internal Reference Clocks..................................................................................................................543 24.4.4 External Reference Clock............................................................................................................................544 24.4.5 MCG Fixed Frequency Clock .....................................................................................................................544 24.
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Section Number Title Page Chapter 26 RTC Oscillator 26.1 26.2 Introduction...................................................................................................................................................................571 26.1.1 Features and Modes.....................................................................................................................................571 26.1.2 Block Diagram.................................................................................
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Section Number 27.5 Title Page 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)..........................................................................595 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................596 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)..........................................................................597 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU).................
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Section Number Title Page 28.4.10 FTFL Command Description.......................................................................................................................626 28.4.11 Security........................................................................................................................................................648 28.4.12 Reset Sequence.................................................................................................................................
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Section Number 29.5 Title Page 29.4.5 Bus Cycle Execution....................................................................................................................................668 29.4.6 FlexBus Timing Examples...........................................................................................................................670 29.4.7 Burst Cycles......................................................................................................................................
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Section Number 31.1.3 31.2 31.3 Title Page Modes of operation......................................................................................................................................710 Memory map and register descriptions.........................................................................................................................710 31.2.1 CRC Data Register (CRC_CRC)................................................................................................................
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Section Number 32.4 Title Page 32.3.8 ADC offset correction register (ADCx_OFS)..............................................................................................737 32.3.9 ADC plus-side gain register (ADCx_PG)....................................................................................................738 32.3.10 ADC minus-side gain register (ADCx_MG)...............................................................................................738 32.3.
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Section Number 32.5 Page 32.4.11 MCU Normal Stop mode operation.............................................................................................................763 32.4.12 MCU Low Power Stop mode operation.......................................................................................................764 Initialization information..............................................................................................................................................764 32.5.
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Section Number Title Page 33.11 Digital to Analog Converter Block Diagram................................................................................................................801 33.12 DAC Functional Description........................................................................................................................................802 33.12.1 Voltage Reference Source Select............................................................................................................
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Section Number 35.1.4 35.2 35.3 35.4 Title Page VREF Signal Descriptions...........................................................................................................................819 Memory Map and Register Definition..........................................................................................................................819 35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................
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Section Number 36.4 36.5 Title Page 36.3.11 Pulse-Out n Enable Register (PDBx_POnEN).............................................................................................839 36.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................839 Functional Description..................................................................................................................................................840 36.4.
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Section Number 37.4 Title Page 37.3.4 Counter (FTMx_CNT).................................................................................................................................861 37.3.5 Modulo (FTMx_MOD)................................................................................................................................862 37.3.6 Channel (n) Status and Control (FTMx_CnSC)...........................................................................................863 37.3.
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Section Number Title Page 37.4.3 Counter.........................................................................................................................................................906 37.4.4 Input Capture Mode.....................................................................................................................................911 37.4.5 Output Compare Mode.......................................................................................................................
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Section Number Title Page 37.6.2 Channel (n) Interrupt....................................................................................................................................980 37.6.3 Fault Interrupt..............................................................................................................................................980 Chapter 38 Periodic Interrupt Timer (PIT) 38.1 Introduction.......................................................................................
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Section Number 39.3.4 39.4 Title Page Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................999 Functional description...................................................................................................................................................1000 39.4.1 LPTMR power and reset..............................................................................................................................1000 39.4.
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Section Number 40.7 40.8 Title Page 40.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)........................................................................1017 40.6.11 CMT Primary Prescaler Register (CMT_PPS)............................................................................................1017 40.6.12 CMT Direct Memory Access (CMT_DMA)...............................................................................................1018 Functional Description.......................
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Section Number Title Page 41.3.3 Compensation...............................................................................................................................................1043 41.3.4 Time alarm...................................................................................................................................................1044 41.3.5 Update mode............................................................................................................................
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Section Number Title Page 42.4.9 Interrupt Status Register (USBx_ISTAT)....................................................................................................1065 42.4.10 Interrupt Enable Register (USBx_INTEN)..................................................................................................1066 42.4.11 Error Interrupt Status Register (USBx_ERRSTAT)....................................................................................1067 42.4.
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Section Number 43.1.3 43.2 43.3 43.5 Page Glossary.......................................................................................................................................................1090 Introduction...................................................................................................................................................................1090 43.2.1 Block Diagram....................................................................................................
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Section Number 44.2 Title Page USB Voltage Regulator Module Signal Descriptions..................................................................................................1117 Chapter 45 CAN (FlexCAN) 45.1 45.2 45.3 Introduction...................................................................................................................................................................1119 45.1.1 Overview.......................................................................................
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Section Number 45.4 45.5 Title Page 45.3.19 Rx Individual Mask Registers (CANx_RXIMRn).......................................................................................1159 45.3.56 Message Buffer Structure.............................................................................................................................1160 45.3.57 Rx FIFO Structure........................................................................................................................................
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Section Number 46.3 46.4 46.5 Title Page 46.2.5 SIN — Serial Input......................................................................................................................................1209 46.2.6 SOUT — Serial Output................................................................................................................................1209 46.2.7 SCK — Serial Clock...............................................................................................................
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Section Number 46.5.5 Title Page Calculation of FIFO Pointer Addresses.......................................................................................................1253 Chapter 47 Inter-Integrated Circuit (I2C) 47.1 Introduction...................................................................................................................................................................1257 47.1.1 Features......................................................................................
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Section Number 47.5 Title Page 47.4.8 Address Matching Wakeup..........................................................................................................................1284 47.4.9 DMA Support...............................................................................................................................................1285 Initialization/Application Information................................................................................................................
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Section Number 48.4 Title Page 48.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO).............................................................................1324 48.3.20 UART FIFO Transmit Count (UARTx_TCFIFO).......................................................................................1324 48.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)...............................................................................1325 48.3.22 UART FIFO Receive Count (UARTx_RCFIFO)..................
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Section Number Title Page 48.8.2 ISO-7816 initialization sequence.................................................................................................................1369 48.8.3 Initialization sequence (non ISO-7816).......................................................................................................1371 48.8.4 Overrun (OR) flag implications...................................................................................................................1372 48.8.
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Section Number 49.5 49.6 Title Page 49.4.11 Protocol Control Register (SDHC_PROCTL).............................................................................................1398 49.4.12 System Control Register (SDHC_SYSCTL)...............................................................................................1402 49.4.13 Interrupt Status Register (SDHC_IRQSTAT).............................................................................................1405 49.4.
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Section Number 49.7 Title Page 49.6.2 Card identification mode..............................................................................................................................1452 49.6.3 Card access...................................................................................................................................................1457 49.6.4 Switch function......................................................................................................................
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Section Number 50.4 50.5 Title Page 50.3.7 I2S Interrupt Enable Register (I2Sx_IER)....................................................................................................1505 50.3.8 I2S Transmit Configuration Register (I2Sx_TCR).......................................................................................1509 50.3.9 I2S Receive Configuration Register (I2Sx_RCR)........................................................................................1511 50.3.
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Section Number 51.2 51.3 Title Page 51.1.2 Modes of operation......................................................................................................................................1557 51.1.3 GPIO signal descriptions.............................................................................................................................1558 Memory map and register definition............................................................................................................
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Section Number 52.7 52.8 Title Page 52.6.2 SCAN control register (TSIx_SCANC).......................................................................................................1577 52.6.3 Pin enable register (TSIx_PEN)...................................................................................................................1580 52.6.4 Status Register (TSIx_STATUS).................................................................................................................1583 52.6.
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Section Number 53.4 53.5 Title Page Functional description...................................................................................................................................................1603 53.4.1 JTAGC reset configuration..........................................................................................................................1603 53.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port.........................................................................................
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Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K20 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K20 microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number.
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Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown.
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Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis portfolio and K20 family of products. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 K20 Family Introduction The K20 MCU family is pin, peripheral and software compatible with the K10 MCU family and adds full and high-speed USB 2.0 On-The-Go with device charger detect capability.
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Module Functional Categories Table 2-1.
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Chapter 2 Introduction 2.3.1 ARM Cortex-M4 Core Modules The following core modules are available on this device. Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM Cortex-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments.
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Module Functional Categories Table 2-3. System modules (continued) Module Description Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details.
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Chapter 2 Introduction Table 2-4. Memories and memory interfaces (continued) Module Description Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industrystandard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming.
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Module Functional Categories Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) 16-bit successive-approximation ADC designed with integrated programmable and programmable-gain amplifiers gain amplifiers (PGA) (PGA) Analog comparators Compares two analog input voltages across the full range of the supply voltage.
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Chapter 2 Introduction Table 2-8.
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Orderable part numbers Table 2-9. Communication modules Module Description USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes. Includes an on-chip transceiver for full and low speeds. USB Device Charger Detect (USBDCD) The USBDCD monitors the USB data lines to detect a smart charger meeting the USB Battery Charging Specification Rev1.1. This information allows the MCU to better manage the battery charging IC in a portable device.
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Chapter 2 Introduction Table 2-11. Orderable part numbers summary Freescale part number CPU frequenc y Pin count Package Total flash memory Program flash EEPROM SRAM GPIO MK20DX256ZVLK10 100 MHz 80 LQFP 512 KB 256 KB 4 KB 64 KB 52 MK20DN512ZVLK10 100 MHz 80 LQFP 512 KB 512 KB — 128 KB 52 MK20DX256ZVMB10 100 MHz 81 MAPBGA 512 KB 256 KB 4 KB 64 KB 52 MK20DN512ZVMB10 100 MHz 81 MAPBGA 512 KB 512 KB — 128 KB 52 K20 Sub-Family Reference Manual, Rev.
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Orderable part numbers K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 64 Freescale Semiconductor, Inc.
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Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and • links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip.
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Core modules Debug Interrupts PPB ARM Cortex-M4 Core Crossbar switch PPB Modules SRAM Upper SRAM Lower Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, r0p0 http://www.arm.
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Chapter 3 Chip Configuration Bus name Description Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. In addition, the CODE bus is also Data code (DCODE) bus tightly coupled to the lower half of the system RAM (SRAM_L). System bus The system bus is connected to a separate master port on the crossbar. In addition, the system bus is tightly coupled to the upper half system RAM (SRAM_U).
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Core modules 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. ARM Cortex-M4 core Interrupts Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-2.
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Chapter 3 Chip Configuration 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4.
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Core modules Table 3-4. Interrupt vector assignments (continued) Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_0054 21 5 0 1 DMA DMA channel 5 transfer complete 0x0000_0058 22 6 0 1 DMA DMA channel 6 transfer complete 0x0000_005C 23 7 0 1 DMA DMA channel 7 transfer complete 0x0000_0060 24 8 0 2 DMA DMA channel 8 transfer complete 0x0000_0064 25 9 0 2 DMA DMA channel 9 transfer complete .
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Chapter 3 Chip Configuration Table 3-4.
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Core modules Table 3-4.
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Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_01A8 106 90 2 22 Port control module Pin detect (Port D) 0x0000_01AC 107 91 2 22 Port control module Pin detect (Port E) 0x0000_01B0 108 92 2 23 — — 0x0000_01B4 109 93 2 23 — — 0x0000_01B8 110 94 2 23 Software Software interrupt4 1.
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Core modules • NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit location = IRQ mod 32 = 21 • NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21 bitfield range is 12-15 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • • • • • • NVICISER2[21] NVICICER2[21] NVICISPR2[21] NVICICPR2[21] NVICIABR2[21] NVICIPR21[15:12] 3.2.
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Chapter 3 Chip Configuration Table 3-6. Reference links to related information (continued) Topic Related module Wake-up requests Reference AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7.
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JTAG controller Signal multiplexing cJTAG System modules Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration 3.3.2 Mode Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Resets Mode controller Power management controller (PMC) Register access Figure 3-6. Mode controller configuration Table 3-10.
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System modules Peripheral bridge Mode controller Register access Power management controller (PMC) Figure 3-7. PMC configuration Table 3-11. Reference links to related information Topic Related module Reference Full description PMC PMC System memory map System memory map Power management Power management Full description Mode Controller Mode Controller Low-Leakage Wakeup Unit (LLWU) LLWU 3.3.
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Chapter 3 Chip Configuration Table 3-12. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) Mode Controller Mode Controller Wake-up requests LLWU wake-up sources 3.3.4.
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System modules up the MCU from any non-VLLSx mode with the NMI function selected in its port control register asserts an NMI exception on low power mode recovery. The same occurs when recovering from VLLSx modes if EzPort is disabled; otherwise, EzPort mode is entered. See the "EzPort Configuration" section in this chapter for more information. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input.
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Chapter 3 Chip Configuration Master Modules Slave Modules Crossbar Switch M1 ARM core system bus M2 Mux S1 DMA Memory protection unit (MPU) S0 M0 ARM core code bus SRAM backdoor Peripheral bridge 0 S2 EzPort Flash controller S3 Mux Peripheral bridge 1 GPIO controller MPU FlexBus M5 S4 M4 USB SDHC Figure 3-10. Crossbar switch integration Table 3-15.
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System modules Table 3-15. Reference links to related information (continued) Topic Related module Reference Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus FlexBus 3.3.6.1 Crossbar Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus 0 ARM core system bus 1 DMA/EzPort 2 USB OTG 4 SDHC 5 NOTE The DMA and EzPort share a master port.
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Chapter 3 Chip Configuration 3.3.7 Memory Protection Unit (MPU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Logical Master Transfers Transfers Logical Master Memory Protection Unit (MPU) Slave Slave Logical Master Slave Figure 3-11. Memory Protection Unit configuration Table 3-16.
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System modules 3.3.7.2 MPU Logical Bus Master Assignments The logical bus master assignments for the MPU are: Table 3-18. MPU Logical Bus Master Assignments MPU Logical Bus Master Number Bus Master 0 Core 1 Debugger 2 DMA 3 none 4 USB 5 SDHC 6 none 7 none 3.3.7.3 MPU Access Violation Indications Access violations detected by the MPU are signaled to the appropriate bus master as shown below: Table 3-19.
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Chapter 3 Chip Configuration Table 3-20. Reset Values for RGD0 Registers Register Reset value RGD0_WORD0 0000_0000h RGD0_WORD1 FFFF_FFFFh RGD0_WORD2 0061_F7DFh RGD0_WORD3 0000_0001h RGDAAC0 0061_F7DFh 3.3.7.5 Write Access Restrictions for RGD0 Registers In addition to configuring the initial state of RGD0, the MPU implements further access control on writes to the RGD0 registers.
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Transfers Transfers AIPS-Lite peripheral bridge Peripherals Crossbar switch System modules Figure 3-12. Peripheral bridge configuration Table 3-22. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch 3.3.8.
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Chapter 3 Chip Configuration 3.3.8.5 PACR registers Each of the two peripheral bridges support up to 128 peripherals each assigned to an PACRx field within the PACRA-PACRP registers. However, fewer peripherals are supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of the peripheral slot assignments for this device. Unused PACRx fields are reserved. 3.3.8.
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System modules 3.3.9.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel. Table 3-24.
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Chapter 3 Chip Configuration Table 3-24.
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System modules Table 3-24. DMA request sources - MUX 0 (continued) Source number Source module Source description 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. 3.3.9.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments . 3.3.
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Chapter 3 Chip Configuration 3.3.11 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 External Watchdog Monitor (EWM) Module signals Signal multiplexing Register access Figure 3-15. External Watchdog Monitor configuration Table 3-26.
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System modules Table 3-28. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS Power Down VLLS3, VLLS2, VLLS1 3.3.11.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device.
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Chapter 3 Chip Configuration 3.3.12.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-30. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.12.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-31.
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Clock Modules Peripheral bridge System integration module (SIM) RTC System oscillator oscillator Register access Multipurpose Clock Generator (MCG) Figure 3-17. MCG configuration Table 3-32. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.
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Chapter 3 Chip Configuration Table 3-33. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.4.
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Memories and Memory Interfaces Peripheral bus controller 0 Flash memory controller Register access Transfers Flash memory Figure 3-20. Flash memory configuration Table 3-35. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.5.1.
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Chapter 3 Chip Configuration Device Program flash (KB) Block 0 (P-Flash) address range1 Block 1 (P-Flash) address range1 MK20DN512ZVLK10 512 0x0000_0000 – 0x0003_FFFF 0x0004_0000 – 0x0007_FFFF MK20DX256ZVMB10 256 0x0000_0000 – 0x0003_FFFF 0x1000_0000 – 0x1003_FFFF MK20DN512ZVMB10 512 0x0000_0000 – 0x0003_FFFF 0x0004_0000 – 0x0007_FFFF 1. The addresses shown assume program flash swap is disabled (default configuration). 3.5.1.
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Memories and Memory Interfaces 3.5.1.6 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory in two ways: 1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for more details. 2. Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes. 3.5.1.
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Chapter 3 Chip Configuration Table 3-36. Reference links to related information (continued) Topic Related module Reference Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar Switch Configuration for details on the master port assignments. 3.5.2.
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Cortex-M4 core MPU Crossbar switch MPU SRAM controller Memories and Memory Interfaces SRAM upper Transfers SRAM lower Figure 3-23. SRAM configuration Table 3-37. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core Memory protection unit Memory protection unit 3.5.3.
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Chapter 3 Chip Configuration Valid address ranges for SRAM_L and SRAM_U are then defined as: • SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF • SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1] This is illustrated in the following figure. SRAM size / 2 SRAM_L SRAM size / 2 0x2000_0000 – SRAM_size/2 SRAM_U 0x1FFF_FFFF 0x2000_0000 0x2000_0000 + SRAM_size/2 - 1 Figure 3-24.
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Memories and Memory Interfaces The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). The following figure illustrates the SRAM accesses within the device. SRAM_L Cortex-M4 core Crossbar switch Frontdoor non-core master Backdoor Code bus non-core master MPU SRAM controller MPU System bus non-core master SRAM_U Figure 3-25.
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Chapter 3 Chip Configuration 3.5.4 SRAM Controller Configuration Cortex-M4 core MPU Crossbar switch Transfers SRAM lower SRAM controller SRAM upper This section summarizes how the module has been configured in the chip. MPU Figure 3-26. SRAM controller configuration Table 3-38.
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Memories and Memory Interfaces Peripheral bridge 0 Register access Register file Figure 3-27. System Register file configuration Table 3-39. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.5.1 System Register file This device includes a 32-byte register file that is powered in all power modes.
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Chapter 3 Chip Configuration Peripheral bridge Register access VBAT register file Figure 3-28. VBAT Register file configuration Table 3-40. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.6.1 VBAT register file This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT.
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Memories and Memory Interfaces Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.7.1 JTAG instruction The system JTAG controller implements an EZPORT instruction.
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Chapter 3 Chip Configuration Peripheral bridge 0 Transfers FlexBus Module signals Signal multiplexing Crossbar switch Memory protection unit Register access Figure 3-30. FlexBus configuration Table 3-42.
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Memories and Memory Interfaces Reserved FB_CS4 FB_TSIZ0 FB_BE_31_24 Group2 Reserved FB_CS5 FB_TSIZ1 FB_BE_23_16 Group3 Reserved FB_TBST FB_CS2 FB_BE_15_8 Group4 Reserved FB_TA FB_CS3 FB_BE_7_0 Group5 External Pins Group1 To other modules FB_TS To other modules FB_CS1 To other modules FB_ALE To other modules CSPMCR Port Control Module To other modules FlexBus Reserved Figure 3-31. FlexBus control signal multiplexing K20 Sub-Family Reference Manual, Rev.
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Chapter 3 Chip Configuration Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function. 3.5.8.3 FlexBus CSCR0 reset value On this device the CSCR0 resets to 0x003F_FC00. Configure this register as needed before performing any FlexBus access.
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Analog Peripheral bridge Register access CRC Figure 3-32. CRC configuration Table 3-43. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC with PGA Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration Table 3-44. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains two ADCs. Each ADC contains a PGA channel for a total of two separate PGAs. 3.7.1.1.
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Analog 3.7.1.3.
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Chapter 3 Chip Configuration 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC1_SE8 7. Interleaved with ADC1_SE9 8. Interleaved with ADC1_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit.
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Analog ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10011 AD19 Reserved ADC1_DM08 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved 10111 AD23 Reserved 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) 11011 AD27 Bandgap (Diff)9 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.
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Chapter 3 Chip Configuration 3.7.1.6 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. ADC0 ADC0_SE8/ADC1_SE8 AD8 ADC0_SE9/ADC1_SE9 AD9 AD8 ADC1 AD9 Figure 3-35. ADC hardware interleaved channels integration 3.7.1.7 ADC and PGA Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • 1.
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Analog 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB.
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Chapter 3 Chip Configuration 3.7.1.
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Analog Peripheral bridge 0 Other peripherals CMP Module signals Signal multiplexing Register access Figure 3-37. CMP configuration Table 3-46. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.
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Chapter 3 Chip Configuration 3.7.2.3 External window/sample input PDB pulse-out controls the CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Transfers Other peripherals 12-bit DAC Module signals Signal multiplexing Register access Figure 3-38. 12-bit DAC configuration Table 3-47.
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Analog 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. 3.7.4 VREF Configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be connected to an output load capacitor. Refer the device data sheet for more details. 3.8 Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip.
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Timers 3.8.1.1.1 3.8.1.1.2 PDB Output Triggers Table 3-50. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Number of DAC triggers 1 Number of PulseOut 1 PDB Input Trigger Connections Table 3-51.
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Chapter 3 Chip Configuration 3.8.1.
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Timers NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. 3.8.1.6 Pulse-Out Connection The Pulse-Out of PDB is connected to all the CMP blocks and used as the sample window. 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-52.
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Chapter 3 Chip Configuration Peripheral bus controller 0 Transfers FlexTimer Other peripherals Module signals Signal multiplexing Register access Figure 3-42. FlexTimer configuration Table 3-53. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.2.
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Timers 3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SOPT4 register in the SIM module. 3.8.2.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK. 3.8.2.
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Chapter 3 Chip Configuration • FTM0 hardware trigger 0 = CMP0 Output • FTM0 hardware trigger 1 = PDB channel 1 Trigger Output • FTM0 hardware trigger 2 = FTM0_FLT0 pin • FTM1 hardware trigger 0 = CMP0 Output • FTM1 hardware trigger 1 = CMP1 Output • FTM1 hardware trigger 2 = FTM1_FLT0 pin • FTM2 hardware trigger 0 = CMP0 Output • FTM2 hardware trigger 1 = CMP2 Output • FTM2 hardware trigger 2 = FTM2_FLT0 pin 3.8.2.
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Timers FTM1 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM0 CONF Register GTBEOUT = 1 GTBEEN = 1 FTM Counter gtb_in gtb_in FTM Counter FTM2 gtb_out CONF Register GTBEOUT = 0 GTBEEN = 1 FTM Counter gtb_in Figure 3-43. FTM Global Time Base Configuration 3.8.2.10 FTM BDM and debug halt mode In the FTM chapter, references to the chip being in "BDM" are the same as the chip being in “debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-56. PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3 3.8.3.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module.
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Timers Table 3-57. Reference links to related information (continued) Topic Related module Reference Power management Signal Multiplexing Power management Port control Signal Multiplexing 3.8.4.1 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield.
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Chapter 3 Chip Configuration 3.8.5 CMT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 CMT Module signals Signal multiplexing Register access Figure 3-46. CMT configuration Table 3-58.
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Timers 3.8.6 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Module signals Real-time clock Signal multiplexing Register access Figure 3-47. RTC configuration Table 3-59.
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Chapter 3 Chip Configuration 3.9 Communication interfaces 3.9.1 Universal Serial Bus (USB) Subsystem The USB subsystem includes these components: • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification. • USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for host mode functionality. • A 3.3 V regulator. • USB device charger detection module.
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Communication interfaces 3.9.1.2.1 AA/AAA cells power supply The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the USB regulator is enabled to power the USB transceiver. 2 AA Cells VDD To PMC and Pads VOUT33 Cstab TYPE A VBUS Chip VREGIN D+ USB0_DP D- USB0_DM USB Regulator USB XCVR USB Controller Figure 3-49. USB regulator AA cell usecase 3.9.1.2.
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Chapter 3 Chip Configuration VDD To PMC and Pads VOUT33 Cstab Chip TYPE A VBUS Charger Si2301 VREGIN USB Regulator D+ USB XCVR USB0_DP DVSS Li-Ion USB0_DM USB Controller VBUS Sense Charger Detect Figure 3-50. USB regulator Li-ion usecase 3.9.1.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor.
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Communication interfaces 3.9.1.3 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. This can be done by setting the SIM_SOPT1[USBSTBY] bit. 3.9.1.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration Peripheral bridge 0 USB OTG Register access USB Device Charger Detect Figure 3-53. USB DCD configuration Table 3-61. Reference links to related information Topic Related module Reference Full description USB DCD USB DCD System memory map System memory map Clocking Clock Distribution USB controller USB controller 3.9.1.
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Communication interfaces NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.2 CAN Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge FlexCAN Module signals Signal multiplexing Register access Figure 3-55. CAN configuration Table 3-63.
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Chapter 3 Chip Configuration 3.9.2.3 Number of message buffers Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. 3.9.2.4 FlexCAN Clocking 3.9.2.4.1 Clocking Options The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between clocking the FlexCAN from the internal bus clock or the input clock (EXTAL). 3.9.2.4.2 Clock Gating The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits.
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Communication interfaces 3.9.2.6 FlexCAN Operation in Low Power Modes The FlexCAN module is operational in VLPR and VLPW modes. With the 2 MHz bus clock, the fastest supported FlexCAN transfer rate is 256 kbps. The bit timing parameters in the module must be adjusted for the new frequency, but full functionality is possible. The FlexCAN module can be configured to generate a wakeup interrupt in STOP and VLPS modes.
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Chapter 3 Chip Configuration 3.9.3.1 SPI Modules Configuration This device contains two SPI modules. 3.9.3.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2. 3.9.3.3 Number of CTARs SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers.
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Communication interfaces 3.9.3.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-67. SPI PCS signals SPI Module PCS Signals SPI0 SPI_PCS[5:0] SPI1 SPI_PCS[3:0] SPI2 SPI_PCS[1:0] 3.9.3.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 1MHz.
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Chapter 3 Chip Configuration 3.9.3.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. 3.9.3.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.3.
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Communication interfaces Table 3-69. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.4.1 Number of I2C modules This device has two I2C modules. 3.9.5 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration 1. Standard features of all UARTs: • RS-485 support • Hardware flow control (RTS/CTS) • 9-bit UART to support address mark with parity • MSB/LSB configuration on data 2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on the bus clock. The maximum baud rate is 1/16 of related source clock frequency. 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. AMR support on all UARTs.
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Communication interfaces Source UART 0 UART 1 UART 2 UART 3 Receiver overrun x x x x Noise flag x x x x Framing error x x x x Parity error x x x x Transmitter buffer overflow x x x x Receiver buffer underflow x x x x Transmit threshold (ISO7816) x — — — Receiver threshold (ISO7816) x — — — Wait timer (ISO7816) x — — — Character wait timer (ISO7816) x — — — Block wait timer (ISO7816) x — — — Guard time violation (ISO7816) x — — — 3.9.
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Chapter 3 Chip Configuration Table 3-71. Reference links to related information (continued) Topic Related module Reference Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.9.6.1 SDHC clocking In addition to the system clock, the SDHC needs a clock for the base for the external card clock.
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Communication interfaces Peripheral bridge I2 S Module signals Signal multiplexing Register access Figure 3-60. I2S configuration Table 3-72. Reference links to related information Topic Related module Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing NOTE The I2S master clock can be output on the I2S0_MCLK pin or input on the I2S0_CLKIN pin.
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Chapter 3 Chip Configuration 3.9.7.3 I2S clock generation To generate the desired frequencies for the I2S module there are multiple clocking options as shown below: • The core/system clock is routed to an 8-bit fractional divider to generate the I2S clock. • The PLL output is routed to an 8-bit fractional divider to generate the I2S clock. • The EXTAL pin directly drives the I2S clock. • The I2S0_CLKIN pin directly drives the I2S clock.
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Human-machine interfaces (HMI) Peripheral bridge Transfers Module signals GPIO controller Signal multiplexing Crossbar switch Register access Figure 3-61. GPIO configuration Table 3-73. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.
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Chapter 3 Chip Configuration Peripheral bridge Touch sense input module Module signals Signal multiplexing Register access Figure 3-62. TSI configuration Table 3-74. Reference links to related information Topic Related module Reference Full description TSI TSI System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.10.2.
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Human-machine interfaces (HMI) Table 3-75.
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Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
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System memory map Table 4-1.
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Chapter 4 Memory Map • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Bit-band region 31 Alias bit-band region 31 0 32 MByte 1 MByte 0 Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.
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SRAM memory map Flash memory base address Registers Program flash base address Flash configuration field Program flash Programming acceleration RAM base address RAM Figure 4-2. Flash memory map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location.
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Chapter 4 Memory Map 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps The peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges (AIPS-Lite 0 and 1): • AIPS-Lite0 covers 512 KB • AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output module (GPIO) AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations 0x4000_0000–0x4007_FFFF.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2.
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Chapter 4 Memory Map Table 4-2.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2.
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Chapter 4 Memory Map Table 4-2.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3.
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Chapter 4 Memory Map Table 4-3.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3.
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Chapter 4 Memory Map Table 4-3.
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Private Peripheral Bus (PPB) memory map Table 4-4.
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Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock.
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Clock definitions OSC MCG SIM Muliplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx SIM 4 MHz IRC ÷2 MCGIRCLK CG 32 kHz IRC MCGFFCLK ÷2 FLL OUTDIV1 CG Core / system clocks OUTDIV2 CG Bus clock OUTDIV3 CG FlexBus clock OUTDIV4 CG Flash clock MCGOUTCLK PLL MCGFLLCLK FRDIV MCGPLLCLK MCGPLLCLK/ MCGFLLCLK System oscillator EXTAL OSCCLK XTAL_CLK XTAL EXTAL32 XTAL32 OSC logic OSCERCLK CG Clock options for so
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Chapter 5 Clock Distribution Clock name Description Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK MCG output of the slow internal reference clock or a divided MCG external reference clock.
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Clock definitions Table 5-1.
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Chapter 5 Clock Distribution 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module’s CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1. The core and system clock frequencies must be 100 MHz or slower. 2. The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock. 3.
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Clock Gating 5.5.1 Clock divider values after reset Each clock divider is programmed via the SIM module’s CLKDIVn registers.
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Chapter 5 Clock Distribution 5.7 Module clocks The following table summarizes the clocks associated with each module. Table 5-2.
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Module clocks Table 5-2.
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Chapter 5 Clock Distribution 5.7.2 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. LPO WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.3 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. MCGOUTCLK TRACECLKIN TPIU TRACE_CLKOUT ÷2 Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3.
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Module clocks NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. Bus clock PORTx digital input filter clock LPO PORTx_DFCR[CS] Figure 5-4. PORTx digital input filter clock generation 5.7.5 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes.
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Chapter 5 Clock Distribution NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. USB_CLKIN USB 48MHz SIM_CLKDIV2 [USBFRAC, USBDIV] MCGPLLCLK or MCGFLLCLK SIM_SOPT2[USBSRC] Figure 5-6. USB 48 MHz clock source 5.7.7 FlexCAN clocking The clock for the FlexCAN's protocol engine can be selected as shown in the following figure.
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Module clocks 5.7.9 SDHC clocking The SDHC module has four possible clock sources for the external clock source, as shown in the following figure. Core / system clock MCGPLLCLK or MCGFLLCLK SDHC clock OSCERCLK SDHC0_CLKIN SIM_SOPT2[SDHCSRC] Figure 5-8. SDHC clock generation 5.7.10 I2S clocking In addition to the bus clock, the I2S has a clock source for master clock generation. The maximum frequency of this clock is 50 MHz.
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Chapter 5 Clock Distribution Bus clock TSI clock in active mode MCGIRCLK OSCERCLK TSI_SCANC[AMCLKS] Figure 5-10. TSI clock generation In low-power mode, the TSI can be clocked as shown in the following figure. NOTE In the TSI chapter, these two clocks are referred to as LPOCLK and VLPOSCCLK. LPO TSI clock in low-power mode ERCLK32K TSI_GENCS[LPCLKS] Figure 5-11. TSI low-power clock generation K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Module clocks K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 180 Freescale Semiconductor, Inc.
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Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1.
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Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRSL register are set following a POR. 6.2.
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Chapter 6 Reset and Boot 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the SRSL[PIN] bit is set. 6.2.2.1.1 Reset pin filter The RESET pin supports digital filtering in all modes of operation. For LLS and VLLSx modes, the LLWU provides an optional fixed digital filter running off the 1 kHz LPO clock. See the LLWU chapter for operation of this filter.
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Reset The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDSC1[LVDRE]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage rises above the low voltage detection threshold. The SRSL[LVD] bit is set following an LVD reset or POR. 6.2.2.
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Chapter 6 Reset and Boot The MC_SRSL[LOC] bit is set to indicate the error. 6.2.2.6 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module.
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Reset 6.2.3 Debug resets The following sections detail the debug resets available on the device. 6.2.3.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the SRSH[JTAG] bit to set. 6.2.3.2 nTRST reset The nTRST pin causes a reset of the JTAG logic when asserted.
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Chapter 6 Reset and Boot • • • • • • DWT ITM NVIC Crossbar bus switch1 AHB-AP1 Private peripheral bus1 6.3 Boot This section describes the boot sequence, including sources and options. 6.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash. 6.3.2 Boot options The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset.
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Boot reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in the following table. Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions Bit Num Field 7-2 Reserved 1 EZPORT_DIS 0 LPBOOT Value Definition Reserved for future expansion. 0 EzPort operation is disabled.
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Chapter 6 Reset and Boot 4. The RESET pin is released, but the system reset of internal logic continues to be held until the Flash Controller finishes initialization. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming FTFL_FOPT[EZPORT_DIS].
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Boot K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 190 Freescale Semiconductor, Inc.
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Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed.
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Power modes Table 7-1. Chip power modes (continued) Chip mode Description Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped.
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Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode BAT (backup battery only) Description Core mode Normal recovery method Off Power-up Sequence The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.
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Power mode transitions 7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application.
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Chapter 7 Power Management 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction.
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Module Operation in Low Power Modes • powered = Memory is powered to retain contents. • low power = Flash has a low power state that retains configuration registers to support faster wakeup. • OFF = Modules are powered off; module is in reset state upon wakeup. • wakeup = Modules can serve as a wakeup source for the chip. Table 7-2.
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Chapter 7 Power Management Table 7-2.
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Clock Gating Table 7-2. Module operation in low power modes (continued) Modules TSI Stop VLPR VLPW VLPS LLS VLLSx wakeup FF FF wakeup wakeup6 wakeup6 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2.
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Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources.
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Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface.
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Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Security Interactions with other Modules K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 202 Freescale Semiconductor, Inc.
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Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: • • • • IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface The basic Cortex-M4 debug architecture is very flexible.
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Introduction INTNMI INTISR[239:0] SLEEPING Cortex-M4 Interrupts Sleep NVIC Core ETM Debug SLEEPDEEP Instr. Trigger Data ETB AWIC Trace port (serial wire or multi-pin) TPIU MCM FPB DWT ITM Private Peripheral Bus (internal) ROM Table APB i/f I-code bus Bus Matrix SW/ JTAG SWJ-DP D-code bus Code bus System bus AHB-AP MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1.
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Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4 seems to be accepted) FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
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The Debug Port IR==BYPASSor IDCODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] A TDI nTRST TCK TMS TDO TRACESWO TDO TDI TDO TDI (1’b1 = 4-pin JTAG) (1’b0 = 2-pin cJTAG) To Test Resources CJTAG TDI TDO PEN TDO TDI nSYS_TDO nSYS_TDI nTRST 1’b1 SWCLKTCK TCK JTAGC nSYS_TRST TCK TMS_OUT TMS_OUT_OE SWDITMS nSYS_TCK nSYS_TMS AHB-AP JTAGir[3:0] TMS_IN IR==BYPASSor IDCODE JTAGNSW A DAP Bus 4’b1111 or 4’b1110 MDM-AP TMS SWDO SWDOEN SWDSEL JTAGSEL SWDITMS SWCLKTCK SWD/ JTAG SELECT Figure
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Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2.
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JTAG status and control registers 9.4.1 IR Codes Table 9-3.
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Chapter 9 Debug It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4.
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JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit 0 Secure1 Name Flash Mass Erase in Progress Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug.
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Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Bit 7 Secure1 Name LLS, VLLSx Status Acknowledge N Description Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8– 31 Reserved for future use N 1. Command available in secure mode 9.5.
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Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Bit 7 Name LP Enabled Description Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state.
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Chapter 9 Debug • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command. • System POR reset Conversely the debug system is capable of generating system reset using the following mechanism: • A system reset in the DAP control register which allows the debugger to hold the system in reset.
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ITM 9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1.
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Chapter 9 Debug 9.11 Coresight Embedded Trace Buffer (ETB) The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from any CoreSight-compliant component trace source with an ATB master port, such as a trace source or a trace funnel. It is included in this device to remove dependencies from the trace pin pad speed, and enable low cost trace solutions. The TraceRAM size is 2 KB.
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TPIU multiple sequential runs by executing code until the ETB is almost full, and halting or executing an interrupt handler to allow the buffer to be emptied, and then continuing executing code. The target halts or executes an interrupt handler when the buffer is almost full to empty the data and then the debugger runs the target again. 9.11.
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Chapter 9 Debug • Sleep cycles • CPI (all instruction cycles except for the first cycle) • Interrupt overhead NOTE An event is emitted each time a counter overflows. • The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information. 9.14 Debug in Low Power Modes In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode.
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Debug & Security 9.14.1 Debug Module State in Low Power Modes The following table shows the state of the debug modules in low power modes. These terms are used: • FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. • static = Module register states and associated memories are retained. • OFF = Modules are powered off; module is in reset state upon wakeup. Table 9-7.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.
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Pinout Table 10-1. Reference links to related information (continued) Topic Related module Clocking Reference Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details. • Each 32-pin port is assigned one interrupt. • The digital filter option has two clock source options: bus clock and 1-kHz LPO.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.3.1 K20 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 81-pin ballmap assignments are currently being developed. The • in the entries in this package column indicate which signals are present on the package.
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Pinout 81 80 MAP LQF BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort F5 17 VDDA VDDA VDDA G5 18 VREFH VREFH VREFH G6 19 VREFL VREFL VREFL F6 20 VSSA VSSA VSSA L3 21 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1 8 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1 8 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1 8 K5 22 DAC0_OUT/ CMP1_IN3/ ADC0_SE2 3 DAC0_OUT/ CMP1_IN3/ ADC0_SE2 3 DAC0_OUT/ CMP1_IN3/ ADC0_SE2 3 L4 23 XTAL32 XTAL32 XTAL32 L5 24 EXTAL32 EXTAL32 EXT
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Chapter 10 Signal Multiplexing and Signal Descriptions 81 80 MAP LQF BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 L11 40 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN 0 K11 41 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN 1 LPT0_ALT1 J11 42 RESET_b RESET_b RESET_b G11 43 PTB0/ LLWU_P5 / ADC0_SE8/ ADC1_SE8/ TSI0_CH0 / PTB0/ ADC0_SE8/ LLWU_P5 ADC1_SE8/ TSI0_CH0 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA G10 44 PTB1 / ADC0_SE9/ ADC1_SE9/ TSI0_CH6 / PTB1 ADC0_SE9/ ADC1_SE9/
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Pinout 81 80 MAP LQF BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 — 59 VSS VSS VSS — 60 VDD VDD VDD A8 61 PTC4/ LLWU_P8 PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT D7 62 PTC5/ LLWU_P9 PTC5/ LLWU_P9 SPI0_SCK LPT0_ALT2 FB_AD10 CMP0_OUT C7 63 PTC6/ LLWU_P10 /CMP0_IN0 /CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXT RG FB_AD9 B7 64 PTC7 /CMP0_IN1 /CMP0_IN1 PTC7 SPI0_SIN FB_AD8 A7 65 PTC8 / ADC1_SE4 b/ CMP0_IN2 / ADC1_SE4 b/ CMP0_IN2
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Chapter 10 Signal Multiplexing and Signal Descriptions 81 80 MAP LQF BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 A2 78 PTD5 / ADC0_SE6 b / ADC0_SE6 b PTD5 SPI0_PCS2 UART0_CT S_b FTM0_CH5 FB_AD1 EWM_OUT _b B2 79 PTD6/ LLWU_P15 / ADC0_SE7 b / ADC0_SE7 b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 A1 80 PTD7 PTD7 CMT_IRO FTM0_CH7 L7 — RESERVED RESERVED RESERVED A11 — NC NC NC B11 — NC NC NC C11 — NC NC NC K3 — NC NC NC H4
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Pinout 81 80 MAP LQF BGA P Pin Name Default ALT0 A10 — NC NC NC A9 — NC NC NC B1 — NC NC NC C2 — NC NC NC C1 — NC NC NC D2 — NC NC NC D1 — NC NC NC E1 — NC NC NC ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 10.3.2 K20 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section.
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Chapter 10 Signal Multiplexing and Signal Descriptions 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4 NC NC NC PTC8 PTC4 NC NC NC A B NC PTD6 PTD3 NC NC NC PTC7 PTC3 PTC0 PTB16 NC B C NC NC PTD2 PTC17 PTC11 PTC10 PTC6 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0 PTC16 PTC9 PTC5 PTC1 PTB18 PTB10 NC D E NC PTE2 PTE1 PTE0 VDD VDD VDD NC PTB17 NC NC E F USB0_DP USB0_DM NC PTE3 VDDA VSSA VSS NC NC NC NC F G VOUT33 VREGIN VSS PTE5
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PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC17 PTC16 VDD VSS PTC11 PTC10 PTC9 PTC8 PTC7 PTC6 PTC5 PTC4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Module Signal Description Tables PTB16 VOUT33 11 50 VDD VREGIN 12 49 VSS PGA0_DP/ADC0_DP0/ADC1_DP3 13 48 PTB11 PGA0_DM/ADC0_DM0/ADC1_DM3 14 47 PTB10 PGA1_DP/ADC1_DP0/ADC0_DP3 15 46 PTB3 PGA1_DM/ADC1_DM0/ADC0_DM3 16 45 PTB2 VDDA 17 44 PTB1 VREFH 18 43 PTB0 VREFL 19 42 RESET
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I/O JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10-3.
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Module Signal Description Tables Table 10-5. System Signal Descriptions (continued) Chip signal name Module signal name Description I/O RESET — Reset bi-directional signal I/O VDD — MCU power I VSS — MCU ground I Table 10-6. EWM Signal Descriptions Chip signal name Module signal name EWM_IN EWM_in EWM_OUT EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the CTRL[ASSIN] bit.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-10. FlexBus Signal Descriptions Chip signal name Module signal name Description I/O FB_CLKOUT FB_CLK FlexBus clock output O FB_AD[31:0] FB_D[31:0]/ FB_AD[31:0] In a non-multiplexed configuration, this is the data bus. In a multiplexed configuration this bus is the address/data bus, FB_AD[31:0]. In non-multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24].
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Module Signal Description Tables Table 10-12.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-17. TRIAMP 1 Signal Descriptions Chip signal name Module signal name Description I/O TRI1_DP inp_3v Amplifier positive input terminal I TRI1_DM inn_3v Amplifier negative input terminal I TRI1_OUT out_3v Amplifier output terminal O Table 10-18. VREF Signal Descriptions Chip signal name Module signal name VREF_OUT VREF_OUT Description I/O Internally-generated Voltage Reference output O 10.4.
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Module Signal Description Tables Table 10-23.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-27. UART 1 Signal Descriptions Chip signal name Module signal name Description I/O UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I Table 10-28.
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Module Signal Description Tables Table 10-31. I2S 0 Signal Descriptions Chip signal name Module signal name I2S0_MCLK — I2S0_RX_BCLK SRCK Description I/O Serial master clock output I/O Serial receive clock. SRCK can be used as an input or output. I/O • In asynchronous mode the receiver uses this clock signal and it is always continuous. • In synchronous mode, the STCK port is used instead for clocking in data. I2S0_RX_FS SRFS Serial receive frame Sync.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-32. GPIO Signal Descriptions (continued) Chip signal name Module signal name Description I/O PTB[31:0]1 PORTB[31:0] General purpose input/output I/O PTC[31:0]1 PORTC[31:0] General purpose input/output I/O PTD[31:0]1 PORTD[31:0] General purpose input/output I/O PTE[31:0]1 PORTE[31:0] General purpose input/output I/O 1. The available GPIO pins depends on the specific package.
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Module Signal Description Tables K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 238 Freescale Semiconductor, Inc.
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Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 Overview The port control and interrupt (PORT) module provides support for external interrupt, digital filtering and port control functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
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Introduction • Selectable clock source for digital input filter with 5-bit resolution on filter size • Digital filter is functional in all digital pin muxing modes • Port control • • • • • • Individual pull control registers with pullup, pulldown and pull-disable support Individual drive strength register supporting high and low drive strength Individual slew rate register supporting fast and slow slew rates Individual input passive filter register supporting enabled and disabled Individual open-drain reg
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Chapter 11 Port control and interrupts (PORT) 11.2 External signal description Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device. 11.3 Detailed signal descriptions Table 11-2. PORTx interface-detailed signal descriptions Signal PORTx[31:0] I/O Description I/O External interrupt. State meaning Asserted-pin is logic one. Negated-pin is logic zero.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W 0000_0000h 11.4.1/248 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W 0000_0000h 11.4.1/248 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W 0000_0000h 11.4.1/248 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W 0000_0000h 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page reads zero) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0000_0000h 11.4.4/251 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 32 R/W 0000_0000h 11.4.5/252 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 32 R/W 0000_0000h 11.4.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W 0000_0000h 11.4.1/248 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W 0000_0000h 11.4.1/248 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W 0000_0000h 11.4.1/248 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W 0000_0000h 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_B050 Pin Control Register n (PORTC_PCR20) 32 R/W 0000_0000h 11.4.1/248 4004_B054 Pin Control Register n (PORTC_PCR21) 32 R/W 0000_0000h 11.4.1/248 4004_B058 Pin Control Register n (PORTC_PCR22) 32 R/W 0000_0000h 11.4.1/248 4004_B05C Pin Control Register n (PORTC_PCR23) 32 R/W 0000_0000h 11.4.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_C030 Pin Control Register n (PORTD_PCR12) 32 R/W 0000_0000h 11.4.1/248 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W 0000_0000h 11.4.1/248 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W 0000_0000h 11.4.1/248 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W 0000_0000h 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_D010 Pin Control Register n (PORTE_PCR4) 32 R/W 0000_0000h 11.4.1/248 4004_D014 Pin Control Register n (PORTE_PCR5) 32 R/W 0000_0000h 11.4.1/248 4004_D018 Pin Control Register n (PORTE_PCR6) 32 R/W 0000_0000h 11.4.1/248 4004_D01C Pin Control Register n (PORTE_PCR7) 32 R/W 0000_0000h 11.4.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.4.4/251 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.4.5/252 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.4.6/253 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.4.7/253 11.
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Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 1001 1010 1011 1100 Others 15 LK 14–11 Reserved 10–8 MUX Lock Register 0 1 6 DSE Pin Mux Control The corresponding pin is configured as follows: Drive Strength Enable Drive Strength configuration is valid in all digital pin muxing modes. Open Drain configuration is valid in all digital pin muxing modes. Open Drain output is disabled on the corresponding pin.
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Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description 2 SRE Slew Rate Enable Slew Rate configuration is valid in all digital pin muxing modes. 0 1 1 PE Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. Pull Enable Pull configuration is valid in all digital pin muxing modes.
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Chapter 11 Port control and interrupts (PORT) 11.4.
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Memory map and register definition PORTx_ISFR field descriptions Field Description 31–0 ISF Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the bit. 0 1 Configured interrupt has not been detected. Configured interrupt has been detected.
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Chapter 11 Port control and interrupts (PORT) 11.4.
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Functional description PORTx_DFWR field descriptions Field 31–5 Reserved 4–0 FILT Description This read-only field is reserved and always has the value zero. Filter Length The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches (in clock cycles) the digital filter absorbs for enabled digital filters.
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Chapter 11 Port control and interrupts (PORT) 11.5.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function.
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Functional description During stop mode, the interrupt status flag for any enabled interrupt (but not DMA request) will asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the low power mode. 11.5.4 Digital filter The digital filter capabilities of the PORT module are available in all digital pin muxing modes provided the PORT module is enabled.
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Chapter 12 System integration module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system integration module (SIM) provides system control and chip configuration registers. 12.1.
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Memory map and register definition 12.1.3 SIM Signal Descriptions Table 12-1. SIM Signal Descriptions Signa Description l I/O EZP_ EzPort mode select CS I 12.1.3.1 Detailed signal description Table 12-2.
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Chapter 12 System integration module (SIM) SIM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W Undefined 12.2.1/260 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000h 12.2.2/262 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.3/264 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.
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Memory map and register definition 12.2.1 System Options Register 1 (SIM_SOPT1) The reset value of the SOPT1 register is as follows: Exit from POR and LVD: USBREGEN is set, USBSTBY is cleared, and OSC32KSEL is cleared.
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Chapter 12 System integration module (SIM) SIM_SOPT1 field descriptions (continued) Field 22–20 Reserved 19 OSC32KSEL Description This read-only field is reserved and always has the value zero. 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for TSI and LPTMR. This bit is reset only for POR/LVD. 0 1 System oscillator (OSC32KCLK) RTC oscillator 18–16 Reserved This read-only field is reserved and always has the value zero.
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Memory map and register definition 12.2.2 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks.
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Chapter 12 System integration module (SIM) SIM_SOPT2 field descriptions (continued) Field Description 10 11 OSCERCLK clock External bypass clock (I2S0_CLKIN) 23–22 Reserved This read-only field is reserved and always has the value zero. 21–20 Reserved This read-only field is reserved and always has the value zero. 19 Reserved This read-only field is reserved and always has the value zero. 18 USBSRC USB clock source select Selects the clock source for the USB 48 MHz clock.
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Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description 10 11 7–1 Reserved Off-chip instruction accesses are disallowed. Data accesses are allowed. Off-chip instruction accesses and data accesses are allowed. This read-only field is reserved and always has the value zero. 0 MCGCLKSEL MCG clock select Selects the MCG's external reference clock. 0 1 System oscillator (OSCCLK) 32 kHz RTC oscillator 12.2.
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Chapter 12 System integration module (SIM) SIM_SOPT4 field descriptions (continued) Field 25 FTM1CLKSEL Description FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module.
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Memory map and register definition SIM_SOPT4 field descriptions (continued) Field 7–5 Reserved 4 FTM1FLT0 Description This read-only field is reserved and always has the value zero. FTM1 Fault 0 Select Selects the source of FTM1 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module.
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Chapter 12 System integration module (SIM) 12.2.
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Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description 10 11 UART0_TX pin modulated with FTM2 channel 0 output Reserved 12.2.5 System Options Register 6 (SIM_SOPT6) The reset values of the RSTFLTEN and RSTFLTSEL bits are for power-on reset only. They are unaffected by other reset types.
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Chapter 12 System integration module (SIM) 12.2.
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Memory map and register definition SIM_SOPT7 field descriptions (continued) Field Description 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1011 7 ADC0ALTTRGEN ADC0 alternate trigger enable Enable alternative conversion triggers for ADC0.
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Chapter 12 System integration module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 1101 1110 1011 RTC seconds Low-power timer trigger Unused 12.2.
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Memory map and register definition SIM_SDID field descriptions (continued) Field Description 3–0 PINID Pincount identification Specifies the pincount of the device. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Reserved 32-pin Reserved 48-pin 64-pin 80-pin 81-pin 100-pin 121-pin 144-pin Reserved 196-pin Reserved 256-pin Reserved 12.2.
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Chapter 12 System integration module (SIM) SIM_SCGC1 field descriptions (continued) Field Description 11 Reserved This read-only field is reserved and always has the value zero. 10 Reserved This read-only field is reserved and always has the value zero. 9–0 Reserved This read-only field is reserved and always has the value zero. 12.2.
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Memory map and register definition 12.2.
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Chapter 12 System integration module (SIM) SIM_SCGC3 field descriptions (continued) Field Description 0 1 Clock disabled Clock enabled 16–13 Reserved This read-only field is reserved and always has the value zero. 12 Reserved This read-only field is reserved and always has the value zero. 11–5 Reserved This read-only field is reserved and always has the value zero. 4 FLEXCAN1 FlexCAN1 Clock Gate Control This bit controls the clock gate to the FlexCAN1 module.
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Memory map and register definition SIM_SCGC4 field descriptions (continued) Field 28 LLWU Description LLWU Clock Gate Control This bit controls the clock gate to the LLWU module. 0 1 27–21 Reserved 20 VREF This read-only field is reserved and always has the value zero. VREF Clock Gate Control This bit controls the clock gate to the VREF module. 0 1 19 CMP This bit controls the clock gate to the comparator module. 13 UART3 This bit controls the clock gate to the USB module.
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Chapter 12 System integration module (SIM) SIM_SCGC4 field descriptions (continued) Field Description 0 1 9–8 Reserved 7 I2C1 This read-only field is reserved and always has the value zero. I2C1 Clock Gate Control This bit controls the clock gate to the I2C1 module. 0 1 6 I2C0 Clock disabled Clock enabled Clock disabled Clock enabled I2C0 Clock Gate Control This bit controls the clock gate to the I2C0 module.
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Memory map and register definition 12.2.
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Chapter 12 System integration module (SIM) SIM_SCGC5 field descriptions (continued) Field Description 0 1 9 PORTA Clock disabled Clock enabled Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 1 Clock disabled Clock enabled 8–7 Reserved This read-only field is reserved and always has the value one. 6 Reserved This read-only field is reserved and always has the value zero. 5 TSI TSI Clock Gate Control This bit controls the clock gate to the TSI module.
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Memory map and register definition 12.2.
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Chapter 12 System integration module (SIM) SIM_SCGC6 field descriptions (continued) Field 24 FTM0 Description FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. 0 1 23 PIT PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 1 22 PDB This bit controls the clock gate to the PDB module. 18 CRC This bit controls the clock gate to the USB DCD module. 15 I2S CRC Clock Gate Control This bit controls the clock gate to the CRC module.
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Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description 12 SPI0 SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 1 11–5 Reserved Clock disabled Clock enabled This read-only field is reserved and always has the value zero. 4 FLEXCAN0 FlexCAN0 Clock Gate Control This bit controls the clock gate to the FlexCAN0 module. 0 1 Clock disabled Clock enabled 3–2 Reserved This read-only field is reserved and always has the value zero.
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Chapter 12 System integration module (SIM) SIM_SCGC7 field descriptions Field Description 31–3 Reserved This read-only field is reserved and always has the value zero. 2 MPU MPU Clock Gate Control This bit controls the clock gate to the MPU module. 0 1 1 DMA Clock disabled Clock enabled DMA Clock Gate Control This bit controls the clock gate to the DMA module. 0 1 0 FLEXBUS Clock disabled Clock enabled FlexBus Clock Gate Control This bit controls the clock gate to the FlexBus module.
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Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 27–24 OUTDIV2 Clock 2 output divider value This field sets the divide value for the peripheral clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 23–20 OUTDIV3 Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8.
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Chapter 12 System integration module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 1010 1011 1100 1101 1110 1111 19–16 OUTDIV4 Clock 4 output divider value This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15–0 Reserved Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16.
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Memory map and register definition 12.2.
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Chapter 12 System integration module (SIM) 12.2.17 Flash Configuration Register 1 (SIM_FCFG1) The EESIZE and DEPART filelds are not applicable.
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Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 1000 64 Bytes 1001 32 Bytes 1010-1110 Reserved 1111 0 Bytes For devices without FlexNVM:Reserved 15–12 Reserved This read-only field is reserved and always has the value zero. 11–8 DEPART FlexNVM partition 7–0 Reserved This read-only field is reserved and always has the value zero. Reserved 12.2.
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Chapter 12 System integration module (SIM) SIM_FCFG2 field descriptions Field Description 31 SWAPPFLSH Swap program flash Indicates that swap is active. 0 1 30 Reserved Swap is not active. Swap is active. This read-only field is reserved and always has the value zero. 29–24 MAXADDR0 Max address block 0 This field concatenated with 13 zeros indicates the first invalid address of flash block 0 (program flash 0).
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Memory map and register definition SIM_UIDH field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. 12.2.
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Chapter 12 System integration module (SIM) 12.2.22 Unique Identification Register Low (SIM_UIDL) Address: SIM_UIDL is 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 292 Freescale Semiconductor, Inc.
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Chapter 13 Mode Controller 13.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section discusses the mode controller (MC) which controls power management and reset mechanisms including the various sources of resets on the device.
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Introduction 13.1.2 Modes of Operation The ARM CPU has three primary modes of operation: run, sleep, and deep sleep. The WFI instruction is used to invoke sleep and deep sleep modes. For Freescale microcontrollers, run, wait and stop are the common terminology used for the primary operating modes. The following table shows the translation between the ARM CPU and the MCU power modes.
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Chapter 13 Mode Controller Table 13-1. Power modes (continued) Mode Description VLPR The Core Clock, System Clock and Bus Clocks maximum frequency is restricted to 2MHz max, Flash Clock is restricted to 1MHz. The slow IRC within the MCG must not be enabled when VLPR is entered. VLPW In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off.
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Introduction Any reset VLPW 4 5 1 VLPR Wait 3 Run 6 7 2 Stop VLPS 8 10 11 9 LLS VLLS 3, 2, 1 Figure 13-1. Power Mode State Diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-2. Power mode transition triggers Transition # From To 1 Run Wait Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core.
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Chapter 13 Mode Controller Table 13-2. Power mode transition triggers (continued) Transition # From To 3 Run VLPR Trigger Conditions Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1MHz. AVLP=1, Set RUNM = 10. NOTE: Poll VLPRS bit before transitioning out of VLPR mode. VLPR Run Set RUNM = 00 or Interrupt with LPWUI =1 or Reset. NOTE: Poll REGONS bit before increasing frequency.
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Introduction Table 13-2. Power mode transition triggers (continued) Transition # From To 11 VLPR VLLS(3,2,1) Trigger Conditions LPLLSM = (see PMCTRL register description for VLLS configuration), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, controlled in System Control Register in ARM core 13.1.2.2 Run Modes The device contains two different run modes: • Run • Very low power run (VLPR) 13.1.2.2.1 Run Mode This is the normal operating mode for the device.
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Chapter 13 Mode Controller • • • • RUNM set to 10b to enter VLPR. Flash programming/erasing is not allowed. The slow IRC must not be enabled. All clock monitors must be disabled before entering VLPR. While in VLPR, the regulator is slow responding and cannot handle fast load transitions. Therefore, do not change the clock frequency. This includes a requirement to not modify the module clock enables in the SIM or any clock divider registers. To re-enter normal run mode, simply clear RUNM.
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Introduction 13.1.2.3.1 Wait Mode Wait mode is entered when the ARM core enters the sleep-now or sleep-on-exit modes. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled and clock gating to the peripheral is enabled via the SIM. When an interrupt request occurs, the CPU exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
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Chapter 13 Mode Controller certain asynchronous mode peripherals are operating with the remainer of the MCU powered off. The tradeoffs depend upon the user's application, where power usage and state retention versus functional needs are weighed. The various stop modes are selected by setting the appropriate bits in the power mode protection (PMPROT) and power mode control (PMCTRL) registers.
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Introduction Register in the ARM core forces the MCU into VLPS and hardware sets the LPWUI bit set. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. On transitions from VLPR to VLPS with LPLLSM set to 000b, hardware forces LPLLSM to value of 010b.
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Chapter 13 Mode Controller 13.1.2.4.4 Very Low-Leakage Stop (VLLS3,2,1) Modes This device contains three very low leakage modes: VLLS3, VLLS2, and VLLS1. When a reference applies to all three low leakage modes, VLLS is used. All three of the VLLS modes can be entered from normal run or VLPR. The MCU enters the configured VLLS mode if: • In sleep-now or sleep-on-exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and • The device is configured as per Table 13-2.
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Introduction No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all the debug controls and settings to be powered off.
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Chapter 13 Mode Controller • • • • • Computer operating properly (COP) timer Clock generator (MCG) loss of clock reset (LOC) Low-voltage detect (LVD) Wakeup from very low leakage stop modes, VLLSx Software reset (SW) - by setting SYSRESETREQ bit of the NVIC's Application Interrupt and Reset Control Register • LOCKUP - core in lockup state • EzPort • MDM AP Reset - by setting System Reset Request bit of the MDM AP Control Register Debug reset: • Asserting JTAG_TRST pin Each of the system reset sources, wi
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Introduction 13.1.3.4 Multi-Clock Generator (MCG) Loss-of-Clock (LOC) Reset The MCG module supports an external reference clock. If the clock monitor is enabled (MCG_C6[CME] is set) and the external reference falls below a certain frequency (specified in the MCG_C2[RANGE] field), the MCU resets. If a loss of clock causes a reset, the SRSL[LOC] bit is set. For more details on the clock generator, see Multi-Clock Generator (MCG). 13.1.3.
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Chapter 13 Mode Controller 13.1.3.7 Software (SW) Reset Setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register forces a software reset on the device. A software reset resets of all major components except for debug. When the device is reset by a software reset, the SRSH[SW] bit is set. 13.1.3.8 Lock-Up Reset When the processor’s built-in system state protection hardware detects the core is locked up because of an unrecoverable exception, a lock-up reset occurs.
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Mode Control Memory Map/Register Definition MC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_E000 System Reset Status Register High (MC_SRSH) 8 R/W 00h 13.2.1/308 4007_E001 System Reset Status Register Low (MC_SRSL) 8 R/W 82h 13.2.2/309 4007_E002 Power Mode Protection Register (MC_PMPROT) 8 R/W 00h 13.2.3/310 4007_E003 Power Mode Control Register (MC_PMCTRL) 8 R/W 00h 13.2.4/312 13.2.
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Chapter 13 Mode Controller MC_SRSH field descriptions (continued) Field Description Indicates reset was caused by the ARM core indication of a LOCKUP event. 0 1 0 JTAG Reset not caused by core LOCKUP event Reset caused by core LOCKUP event JTAG generated reset Indicates reset was caused by JTAG selection of certain IR codes (EZPORT, EXTEST, HIGHZ, and CLAMP). 0 1 Reset not caused by JTAG Reset caused by JTAG 13.2.
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Mode Control Memory Map/Register Definition MC_SRSL field descriptions (continued) Field Description 0 1 6 PIN External reset pin Indicates reset was caused by an active-low level on the external RESETpin. 0 1 5 COP 2 LOC Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by disabling the watchdog. For more information, see the watchdog chapter. Loss-of-clock reset Indicates reset was caused by a loss of external clock.
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Chapter 13 Mode Controller If the MCU is configured for a disallowed power mode, the MCU remains in its current power mode. For example, if in normal run (RUNM = 00, AVLP = 0) an attempt to enter VLPR using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b indicating MCU is still in normal run mode. PMPROT is write once after any reset. This write to PMPROT clears LPLLSM, which provides protection after wakeup from low power or low leakage modes.
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Mode Control Memory Map/Register Definition MC_PMPROT field descriptions (continued) Field Description 0 1 1 AVLLS2 Allow very low leakage stop 2 mode This write once bit allows the MCU to enter very low leakage stop 2 mode (VLLS2) provided the appropriate control bits are set up in PMCTRL.
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Chapter 13 Mode Controller Address: MC_PMCTRL is 4007_E000h base + 3h offset = 4007_E003h Bit Read Write Reset 7 6 LPWUI 5 4 RUNM 0 0 3 2 0 0 0 1 0 LPLLSM 0 0 0 0 MC_PMCTRL field descriptions Field 7 LPWUI Description Low Power Wake Up on Interrupt Controls if the voltage regulator exits stop regulation when any active MCU interrupt occurs, returning the MCU to normal run mode.
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Mode Control Memory Map/Register Definition K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 314 Freescale Semiconductor, Inc.
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Chapter 14 Power Management Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PMC contains the internal voltage regulator, power on reset (POR), and low voltage detect system. The Mode Controller controls the PMC and its chapter contains description of all device resets, including POR. 14.
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Low-Voltage Detect (LVD) System selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the internal supply voltage falls below the selected internal monitor trip point (VLVD).
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Chapter 14 Power Management Controller The LVDSC2[LVWV] bits select one of four trip voltages: • Highest (VLVW4) • Two mid-levels (VLVW3 and VLVW2) • Lowest (VLVW1) 14.4 PMC Memory Map/Register Definition The following table shows the registers related to the PMC. See Mode Control Memory Map/Register Definition for the mode controller registers.
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PMC Memory Map/Register Definition Address: PMC_LVDSC1 is 4007_D000h base + 0h offset = 4007_D000h Bit Read 7 6 LVDF 0 Write Reset 5 LVDACK 0 0 4 3 LVDIE LVDRE 0 1 2 1 0 0 0 LVDV 0 0 0 PMC_LVDSC1 field descriptions Field 7 LVDF Description Low-Voltage Detect Flag This read-only status bit indicates a low-voltage detect event. 0 1 6 LVDACK 5 LVDIE Low-Voltage Detect Acknowledge This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF).
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Chapter 14 Power Management Controller See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV bits.
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PMC Memory Map/Register Definition 14.4.3 Regulator Status and Control Register (PMC_REGSC) The power management controller contains an internal voltage regulator. The voltage regulator design uses a bandgap reference, that is also available through a buffer as input to certain internal peripherals. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation.
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Chapter 15 Low-leakage wake-up unit (LLWU) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 7 internal modules as a wakeup source from low-leakage power modes (LLS and VLLS). The input sources vary by device and are described in the specific device's Chip Configuration details. Each of the available wakeup sources can be individually enabled.
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Introduction 15.1.1 Features The LLWU module features include: • Supports up to 16 external input pins and up to 7 internal modules with individual enable bits • Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the Chip Configuration details for wakeup input sources for this device.
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Chapter 15 Low-leakage wake-up unit (LLWU) 15.1.2.2 VLLS modes The LLWU module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. In addition, a VLLS reset event can be initiated via assertion of the RESET pin. All wakeup and reset events result in VLLS exit via a reset flow. 15.1.2.3 Non-low leakage modes The LLWU is not active in all non- LLS and VLLS modes where detection and control logic are in a static state.
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LLWU Signal Descriptions LLS/VLLS entered WUME7 LLWU_MWUF7 occurred Module7 interrupt flag (LLWU_M7IF) (System Error) Interrupt module flag detect Module6 interrupt flag (LLWU_M6IF) Interrupt module flag detect LLWU_MWUF6 occurred Interrupt module flag detect LLWU_MWUF0 occurred WUME6 Module0 interrupt flag (LLWU_M0IF) WUPE15 2 LLWU controller WUME0 LPO LLWU_P15 exit low leakge mode (LLS or VLLS) FLTEP Edge detect interrupt flow Pin filter LLWU_P0 Internal module sources LLWU_P0-LLWU_P1
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Chapter 15 Low-leakage wake-up unit (LLWU) 15.
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Memory map/register definition Address: LLWU_PE1 is 4007_C000h base + 0h offset = 4007_C000h Bit 7 Read 5 WUPE3 Write Reset 6 0 4 3 WUPE2 0 0 2 1 WUPE1 0 0 0 WUPE0 0 0 0 LLWU_PE1 field descriptions Field 7–6 WUPE3 Description Wakeup Pin Enable for LLWU_P3 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5–4 WUPE2 Wakeup Pin Enable for LLWU_P2 Enables and configures the edge detection for the wakeup pin.
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Chapter 15 Low-leakage wake-up unit (LLWU) NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_PE2 is 4007_C000h base + 1h offset = 4007_C001h Bit 7 Read 5 WUPE7 Write Reset 6 0 4 3 WUPE6 0 0 2 1 WUPE5 0 0 0 WUPE4 0 0 0 LLWU_PE2 field descriptions Field 7–6 WUPE7 Description Wakeup Pin Enable for LLWU_P7 Enables and configures the edge detection for the wakeup pin.
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Memory map/register definition 15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3) LLWU_PE3 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS).
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Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description 10 11 External input pin enabled with falling edge detection External input pin enabled with any change detection 15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4) LLWU_PE4 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS).
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Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description 10 11 1–0 WUPE12 External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable for LLWU_P12 Enables and configures the edge detection for the wakeup pin.
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Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_ME field descriptions (continued) Field Description 0 1 4 WUME4 Wakeup Module Enable for Module 4 Enables an internal module as a wakeup source input. 0 1 3 WUME3 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input.
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Memory map/register definition Address: LLWU_F1 is 4007_C000h base + 5h offset = 4007_C005h 7 6 5 4 3 2 1 0 Read Bit WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field 7 WUF7 Description Wakeup Flag for LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF7.
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Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_F1 field descriptions (continued) Field 1 WUF1 Description Wakeup Flag for LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF1. 0 1 0 WUF0 LLWU_P1 input was not a source of wakeup from LLS or VLLS mode LLWU_P1 input was a source of wakeup from LLS or VLLS mode Wakeup Flag for LLWU_P0 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS.
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Memory map/register definition LLWU_F2 field descriptions (continued) Field Description 0 1 6 WUF14 Wakeup Flag for LLWU_P14 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF14. 0 1 5 WUF13 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF13. Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF12.
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Chapter 15 Low-leakage wake-up unit (LLWU) 15.3.8 LLWU Flag 3 Register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this will be the source causing the CPU interrupt flow. For VLLS, this will be the source causing the MCU reset flow. For internal peripherals that are capable of running in LLS or VLLS mode, such as RTC or CMP modules, the flag from the associated peripheral is accessible as the MWUFx bit.
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Memory map/register definition LLWU_F3 field descriptions (continued) Field 4 MWUF4 Description Wakeup flag for module 4 Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism. 0 1 3 MWUF3 Wakeup flag for module 3 Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.
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Chapter 15 Low-leakage wake-up unit (LLWU) Address: LLWU_CS is 4007_C000h base + 8h offset = 4007_C008h Bit 7 6 Read ACKISO Write w1c Reset 0 5 4 3 2 0 1 0 0 0 0 1 1 0 FLTEP FLTR 0 0 LLWU_CS field descriptions Field 7 ACKISO Description Acknowledge Isolation Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode.
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Functional description The LLWU implements an optional 3-cycle glitch filter, based on the LPO clock, such that a detected external pin is required to stay asserted until the enabled glitch filter times out. There is also 2 additional cycles of latency due to synchronization that results in a total of 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled.
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Chapter 15 Low-leakage wake-up unit (LLWU) In the case of a wakeup due to external pin or internal module wakeup, the I/O states are held until software clears the ACKISO bit (by writing a 1 to it). Recovery is always via a system reset flow and the MC_SRS[WAKEUP] is set indicating the low leakage mode was active prior to the last system reset flow. An VLLS reset event due to RESET pin assertion causes an exit via a system reset.
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Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 340 Freescale Semiconductor, Inc.
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Chapter 16 Miscellaneous Control Module (MCM) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 16.1.1 Features The MCM includes these distinctive features: • Program-visible information on the platform configuration and revision • Control and counting logic for ETB almost full 16.
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Memory Map/Register Descriptions MCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page E008_000A Crossbar switch (AXBS) master configuration (MCM_PLAMC) 16 R 003Fh 16.2.2/342 E008_000C SRAM arbitration and protection (MCM_SRAMAP) 32 R/W 0000_0000h 16.2.3/343 E008_0010 Interrupt status register (MCM_ISR) 32 R 0000_0000h 16.2.4/344 E008_0014 ETB counter control register (MCM_ETBCC) 32 R/W 0000_0000h 16.2.
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Chapter 16 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions Field Description 15–8 Reserved This read-only field is reserved and always has the value zero. 7–0 AMC Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port. 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 16.2.
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Memory Map/Register Descriptions MCM_SRAMAP field descriptions (continued) Field Description 01 10 11 27 Reserved Special round robin (favors SRAM backoor accesses over the processor) Fixed priority. Processor has highest, backdoor has lowest Fixed priority. Backdoor has highest, processor has lowest This read-only field is reserved and always has the value zero.
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Chapter 16 Miscellaneous Control Module (MCM) MCM_ISR field descriptions (continued) Field Description 2 NMI Non-maskable interrupt pending If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires. 0 1 1 IRQ No pending NMI Due to the ETB counter expiring, an NMI is pending Normal interrupt pending If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
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Memory Map/Register Descriptions MCM_ETBCC field descriptions (continued) Field Description If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit clears the debug halt request.
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Chapter 16 Miscellaneous Control Module (MCM) 16.2.
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Functional Description 16.3.1.2 Normal interrupt The MCM's normal interrupt is generated if any of the following are true: • MCM_ISCR[ETBI] is set, which is caused by • The ETB counter is enabled (MCM_ETBCC[CNTEN] = 1), • The ETB count expires, and • The response to counter expiration is a normal interrupt (MCM_ETBCC[RSPT] = 01) K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 348 Freescale Semiconductor, Inc.
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Chapter 17 Crossbar Switch (AXBS) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
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Memory Map / Register Definition 17.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and writetransfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode. Additionally, these registers can be read from or written to only by 32-bit accesses. A bus error response is returned if an unimplemented location is accessed within the crossbar switch.
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Chapter 17 Crossbar Switch (AXBS) AXBS memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_4600 Priority Registers Slave (AXBS_PRS6) 32 R/W 7654_3210h 17.2.1/351 4000_4610 Control Register (AXBS_CRS6) 32 R/W 0000_0000h 17.2.2/354 4000_4700 Priority Registers Slave (AXBS_PRS7) 32 R/W 7654_3210h 17.2.1/351 4000_4710 Control Register (AXBS_CRS7) 32 R/W 0000_0000h 17.2.
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Memory Map / Register Definition • If the device contains less than five masters, values 000– 011 are valid and writing other values results in an error. • If the device contains n masters where n ≥ 5, values 0 to n-1 are valid and writing other values results in an error.
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Chapter 17 Crossbar Switch (AXBS) AXBS_PRSn field descriptions (continued) Field 22–20 M5 19 Reserved 18–16 M4 15 Reserved 14–12 M3 11 Reserved 10–8 M2 Description Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 000 001 010 011 100 101 110 111 This master has level 1, or highest, priority when accessing the slave port. This master has level 2 priority when accessing the slave port. This master has level 3 priority when accessing the slave port.
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Memory Map / Register Definition AXBS_PRSn field descriptions (continued) Field Description 7 Reserved This read-only field is reserved and always has the value zero. 6–4 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 000 001 010 011 100 101 110 111 3 Reserved This master has level 1, or highest, priority when accessing the slave port. This master has level 2 priority when accessing the slave port.
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Chapter 17 Crossbar Switch (AXBS) AXBS_CRSn field descriptions Field 31 RO Description Read only Forces the slave port’s CSRn and PRSn registers to be read-only. After set, only a hardware reset clears it. 0 1 30 HLP Halt low priority Sets the initial arbitration priority for low power mode requests. Setting this bit will not effect the request for low power mode from attaining highest priority once it has control of the slave ports.
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Memory Map / Register Definition AXBS_CRSn field descriptions (continued) Field Description 001 010 011 100 101 110 111 Park on master port M1 Park on master port M2 Park on master port M3 Park on master port M4 Park on master port M5 Reserved Reserved 17.2.3 Master General Purpose Control Register (AXBS_MGPCRn) The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters.
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Chapter 17 Crossbar Switch (AXBS) AXBS_MGPCRn field descriptions (continued) Field Description 101 110 111 Reserved Reserved Reserved 17.3 Functional Description 17.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. It is possible to make single-clock, or zero wait state, accesses through the crossbar.
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Functional Description The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave busses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it can park the slave port on the master port indicated by CRSn[PARK].
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Chapter 17 Crossbar Switch (AXBS) MGPCR[AULB] No arbitration Master-to-slave transfer 1 1 beat Lost control Arbitration allowed 2 3 4 5 6 1 beat Lost control No arbitration 7 8 9 10 No arbitration 11 12 12 beat burst Figure 17-28. Undefined length burst example In this example, a master runs an undefined length burst and the MGPCR[AULB] bits indicate arbitration occurs after the fourth beat of the burst.
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Functional Description When a master makes a request to a slave port, the slave port checks if the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: Table 17-29.
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Chapter 17 Crossbar Switch (AXBS) Parking may continue to be used in a round-robin mode, but does not affect the roundrobin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority. 17.3.3.4 Priority assignment Each master port needs to be assigned a unique 3-bit priority level.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 362 Freescale Semiconductor, Inc.
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Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in the device. 18.2 Overview The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and their access rights.
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Overview Slave Port n Address Phase Signals MPU_EARn Internal Peripheral Bus Access Evaluation Macro Region Descriptor 0 Access Evaluation Macro Region Descriptor 1 Access Evaluation Macro Region Descriptor x MPU_EDRn Mux Figure 18-1. MPU Block Diagram 18.2.2 Features The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system.
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Chapter 18 Memory Protection Unit (MPU) • Alternate programming model view of the access control permissions word • Priority given to granting permission over denying access for overlapping region descriptors • Detects access protection errors if a memory reference does not hit in any memory region, or if the reference is illegal in all hit memory regions.
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Memory Map/Register Definition MPU memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_D020 Error Address Register, Slave Port n (MPU_EAR2) 32 R Undefined 18.3.2/370 4000_D024 Error Detail Register, Slave Port n (MPU_EDR2) 32 R Undefined 18.3.3/371 4000_D028 Error Address Register, Slave Port n (MPU_EAR3) 32 R Undefined 18.3.2/370 4000_D02C Error Detail Register, Slave Port n (MPU_EDR3) 32 R Undefined 18.3.
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Chapter 18 Memory Protection Unit (MPU) MPU memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_D46C Region Descriptor n, Word 3 (MPU_RGD6_WORD3) 32 R/W 0000_0000h 18.3.7/376 4000_D470 Region Descriptor n, Word 0 (MPU_RGD7_WORD0) 32 R/W 0000_0000h 18.3.4/372 4000_D474 Region Descriptor n, Word 1 (MPU_RGD7_WORD1) 32 R/W 0000_001Fh 18.3.5/373 4000_D478 Region Descriptor n, Word 2 (MPU_RGD7_WORD2) 32 R/W 0000_0000h 18.3.
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Memory Map/Register Definition MPU memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_D81C Region Descriptor Alternate Access Control n (MPU_RGDAAC7) 32 R/W 0000_0000h 18.3.8/377 4000_D820 Region Descriptor Alternate Access Control n (MPU_RGDAAC8) 32 R/W 0000_0000h 18.3.8/377 4000_D824 Region Descriptor Alternate Access Control n (MPU_RGDAAC9) 32 R/W 0000_0000h 18.3.
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Chapter 18 Memory Protection Unit (MPU) MPU_CESR field descriptions (continued) Field 22–20 Reserved Description This read-only field is reserved and always has the value zero. 19–16 HRL Hardware revision level 15–12 NSP Number of slave ports 11–8 NRGD Number of region descriptors Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. Specifies the number of slave ports connected to the MPU.
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Memory Map/Register Definition 18.3.2 Error Address Register, Slave Port n (MPU_EARn) When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in CESR[SPERR] set. Additional information about the faulting access is captured in the corresponding EDRn at the same time.
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Chapter 18 Memory Protection Unit (MPU) 18.3.3 Error Detail Register, Slave Port n (MPU_EDRn) When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in CESR[SPERR] is set. Information on the faulting address is captured in the corresponding EARn register at the same time.
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Memory Map/Register Definition MPU_EDRn field descriptions (continued) Field Description NOTE: All other encodings are reserved. 000 001 010 011 0 ERW User mode, instruction access User mode, data access Supervisor mode, instruction access Supervisor mode, data access Error read/write Indicates the access type of the faulting reference. 0 1 Read Write 18.3.
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Chapter 18 Memory Protection Unit (MPU) 18.3.5 Region Descriptor n, Word 1 (MPU_RGD_WORD1) The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]).
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Memory Map/Register Definition Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit.
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Chapter 18 Memory Protection Unit (MPU) MPU_RGDn_WORD2 field descriptions (continued) Field Description 0 1 24 M4WE 23 Reserved 22–21 M3SM Bus master 4 write enable 0 1 Bus master 3 supervisor mode access control Defines the access controls for bus master 3 in supervisor mode r/w/x; read, write and execute allowed r/x; read and execute allowed, but no write r/w; read and write allowed, but no execute Same as user mode defined in M3UM Bus master 3 user mode access control Defines the access controls f
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Memory Map/Register Definition MPU_RGDn_WORD2 field descriptions (continued) Field Description See M3UM description 18.3.7 Region Descriptor n, Word 3 (MPU_RGD_WORD3) The fourth word of the region descriptor contains the region descriptor’s valid bit.
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Chapter 18 Memory Protection Unit (MPU) 18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn) Since software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32bit entity is available. Writing to this register does not affect the descriptor’s valid bit.
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Memory Map/Register Definition MPU_RGDAACn field descriptions (continued) Field Description 0 1 Bus master 5 writes terminate with an access error and the write is not performed Bus master 5 writes allowed 25 M4RE Bus master 4 read enable.
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Chapter 18 Memory Protection Unit (MPU) MPU_RGDAACn field descriptions (continued) Field Description 4–3 M0SM Bus master 0 supervisor mode access control 2–0 M0UM Bus master 0 user mode access control See M3SM description. See M3UM description. 18.4 Functional Description In this section, the functional operation of the MPU is detailed, including the operation of the access evaluation macro and the handling of error-terminated bus cycles. 18.4.
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Functional Description 18.4.1.1 Hit Determination To determine if the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses.
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Chapter 18 Memory Protection Unit (MPU) 1. If the access does not hit in any region descriptor, a protection error is reported. 2. If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, a protection error is reported.
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Application Information • Creating a new memory region—Load the appropriate region descriptor into an available RGDn, using four sequential 32-bit writes. The hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/ removes an existing memory region.
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Chapter 18 Memory Protection Unit (MPU) Table 18-81.
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Application Information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 384 Freescale Semiconductor, Inc.
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Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals. The peripheral bridge occupies a 64 MB portion of the address space.
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Memory map/register definition module address, transfer attributes, byte enables, and write data as inputs to the peripherals. The peripheral bridge captures read data from the peripheral interface and drives it to the crossbar switch. The register maps of the peripherals are located on 4 KB boundaries. Each peripheral is allocated one 4 KB block of the memory map. The peripheral bridge (AIPS-Lite) memory map is illustrated as follows.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_0040 Peripheral Access Control Register (AIPS0_PACRE) 32 R/W Undefined 19.2.3/396 4000_0044 Peripheral Access Control Register (AIPS0_PACRF) 32 R/W Undefined 19.2.3/396 4000_0048 Peripheral Access Control Register (AIPS0_PACRG) 32 R/W Undefined 19.2.
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Memory map/register definition NOTE At reset, the default value loaded into the MPROT[7-0] fields is device-specific. See the Chip Configuration details for the value on your particular device. Accesses to registers or register fields which correspond to master or peripheral locations which are not implemented return zeros on reads, and are ignored on writes. Each master is assigned depending on its connection to the crossbar switch master ports.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field 26 MTR1 Description Master trusted for read Determines whether the master is trusted for read accesses. 0 1 25 MTW1 Master trusted for writes Determines whether the master is trusted for write accesses. 0 1 24 MPL1 22 MTR2 Specifies how the privilege level of the master is determined. Master trusted for read Determines whether the master is trusted for read accesses.
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Memory map/register definition AIPSx_MPRA field descriptions (continued) Field Description 0 1 16 MPL3 Master privilege level Specifies how the privilege level of the master is determined. 0 1 15 Reserved 14 MTR4 Master trusted for read Determines whether the master is trusted for read accesses. Determines whether the master is trusted for write accesses. 10 MTR5 Specifies how the privilege level of the master is determined.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field Description 3–0 Reserved This read-only field is reserved and always has the value zero. 19.2.2 Peripheral Access Control Register (AIPSx_PACRn) Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels supported by the given module.
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Memory map/register definition Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 Addresses: AIPS0_PACRA is 4000_0000h base + 20h offset = 400
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field 27 Reserved 26 SP1 Description This read-only field is reserved and always has the value zero. Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description 0 1 19 Reserved 18 SP3 This read-only field is reserved and always has the value zero. Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 1 11 Reserved 10 SP5 This read-only field is reserved and always has the value zero.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field 4 TP6 Description Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 1 3 Reserved 2 SP7 This read-only field is reserved and always has the value zero.
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Chapter 19 Peripheral Bridge (AIPS-Lite) NOTE The reset value of the PACRE-P depends on your device's configuration.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description 0 1 25 WP1 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 1 24 TP1 22 SP2 Determines whether the peripheral allows accesses from an untrusted master.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 1 17 WP3 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 1 9 WP5 Write protect Determines whether the peripheral allows write accesss.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field 2 SP7 Description Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates .
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Functional Description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 402 Freescale Semiconductor, Inc.
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Chapter 20 Direct memory access multiplexer (DMAMUX) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 Overview The DMA Mux routes up to 63 DMA sources (called slots) to be mapped to any of the 16 DMA channels. This is illustrated in the following figure. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Introduction DMAMUX Source #1 DMA Channel #0 DMA Channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA Channel #n Trigger #z Figure 20-1. DMA MUX block diagram 20.1.2 Features The DMA channel MUX provides these features: • 52 peripheral slots + 10 always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. • The first 4 channels additionally provide a trigger functionality.
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Chapter 20 Direct memory access multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place (e.g. changing the period of a DMA trigger).
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Memory map/register definition DMAMUX memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_1000 Channel Configuration Register (DMAMUX_CHCFG0) 8 R/W 00h 20.3.1/406 4002_1001 Channel Configuration Register (DMAMUX_CHCFG1) 8 R/W 00h 20.3.1/406 4002_1002 Channel Configuration Register (DMAMUX_CHCFG2) 8 R/W 00h 20.3.1/406 4002_1003 Channel Configuration Register (DMAMUX_CHCFG3) 8 R/W 00h 20.3.
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Chapter 20 Direct memory access multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions Field 7 ENBL Description DMA Channel Enable Enables the DMA channel 0 1 6 TRIG DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel 0 1 5–0 SOURCE DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
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Functional description such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. Please refer to Periodic Interrupt Timer chapter for more information on this topic. Note Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed.
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Chapter 20 Direct memory access multiplexer (DMAMUX) Peripheral Request Trigger DMA Request Figure 20-20. DMA MUX channel triggering: normal operation Once the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, that triggered will be ignored.
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Functional description 20.4.2 DMA channels with no triggering capability The other channels of the DMA MUX provide the normal routing functionality as described in Modes of operation. 20.4.3 "Always enabled" DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are "always enabled".
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Chapter 20 Direct memory access multiplexer (DMAMUX) • Use explicit software re-activation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to re-activate the channel (by writing to the DMA registers) after every minor loop. For this option, the DMA channel should be disabled in the DMA channel MUX. • Use a "always enabled" DMA source.
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Initialization/application information 3. Configure a timer for the desired trigger interval 4. Write 0xC5 to CHCFG2 (base address + 0x02) The following code example illustrates steps #1 and #4 above: In File registers.
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Chapter 20 Direct memory access multiplexer (DMAMUX) volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned char char char char char char char char char char char char char *CHCONFIG3 = *CHCONFIG4 = *CHCONFIG5 = *CHCONFIG6 = *CHCONFIG7 = *CHCONFIG8 = *CHCONFIG9 = *CHCONFIG10= *CHCONFIG11= *CHCONFIG12= *CHCONFIG13= *CHCONFIG14= *
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Initialization/application information volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned char char char char char char char char *CHCONFIG8 = *CHCONFIG9 = *CHCONFIG10= *CHCONFIG11= *CHCONFIG12= *CHCONFIG13= *CHCONFIG14= *CHCONFIG15= (volatile (volatile (volatile (volatile (volatile (volatile (volatile (volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned char char char char char ch
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Chapter 21 Direct Memory Access Controller (eDMA) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor.
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Introduction eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-1. eDMA block diagram 21.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
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Chapter 21 Direct Memory Access Controller (eDMA) Table 21-1. eDMA engine submodules Submodule Address path Function This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality.
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Introduction Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage is implemented using a single-port, synchronous RAM array. 21.1.
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Chapter 21 Direct Memory Access Controller (eDMA) • Channel completion reported via optional interrupt requests • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures • Support to cancel transfers via software In the discussion of this module, n is used to re
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Memory map/register definition • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented as 11 registers of 16 or 32 bits.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) 4000_801E Register name Width Access (in bits) Clear Error Register (DMA_CERR) Reset value Section/ page 8 W (always reads zero) 00h 21.3.11/ 448 00h 21.3.12/ 449 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads zero) 4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 21.3.13/ 449 4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_810E Channel n Priority Register (DMA_DCHPRI13) 8 R/W Undefined 21.3.16/ 456 4000_810F Channel n Priority Register (DMA_DCHPRI12) 8 R/W Undefined 21.3.16/ 456 4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 21.3.17/ 457 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9028 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD1_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 459 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9054 TCD Signed Destination Address Offset (DMA_TCD2_DOFF) 16 R/W Undefined 21.3.25/ 463 4000_9056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 463 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 468 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 21.3.19/ 458 4000_90A8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD5_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 459 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined 21.3.24/ 462 4000_90D4 TCD Signed Destination Address Offset (DMA_TCD6_DOFF) 16 R/W Undefined 21.3.25/ 463 4000_90D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined 21.3.29/ 466 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_BITER_ELINKYES) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined 21.3.18/ 458 4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined 21.3.19/ 458 4000_9128 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD9_NBYTES_MLNO) 32 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_914C TCD Last Source Address Adjustment (DMA_TCD10_SLAST) 32 R/W Undefined 21.3.23/ 462 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined 21.3.24/ 462 4000_9154 TCD Signed Destination Address Offset (DMA_TCD10_DOFF) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9178 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD11_DLASTSGA) 32 R/W Undefined 21.3.28/ 465 4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined 21.3.17/ 457 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined 21.3.18/ 458 4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 461 4000_91CC TCD Last Source Address Adjustment (DMA_TCD14_SLAST) 32 R/W Undefined 21.3.23/ 462 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 464 4000_91F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD15_DLASTSGA) 32 R/W Undefined 21.3.28/ 465 4000_91FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_CR field descriptions (continued) Field Description 0 1 16 ECX 15–8 Reserved 7 EMLM 6 CLM Normal operation Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
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Memory map/register definition DMA_CR field descriptions (continued) Field Description 0 1 0 Reserved When in debug mode, the DMA continues to operate. When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. This read-only field is reserved and always has the value zero. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ES field descriptions (continued) Field 15 Reserved 14 CPE Description This read-only field is reserved and always has the value zero. Channel Priority Error 0 1 No channel priority error The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique. 13–12 Reserved This read-only field is reserved and always has the value zero.
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Memory map/register definition DMA_ES field descriptions (continued) Field Description 1 SBE Source Bus Error 0 DBE Destination Bus Error 0 1 0 1 No source bus error The last recorded error was a bus error on a source read No destination bus error The last recorded error was a bus error on a destination write 21.3.3 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 16 implemented channels to enable the request signal for each channel.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERQ field descriptions (continued) Field Description 13 ERQ13 Enable DMA Request 13 12 ERQ12 Enable DMA Request 12 11 ERQ11 Enable DMA Request 11 10 ERQ10 Enable DMA Request 10 9 ERQ9 Enable DMA Request 9 8 ERQ8 Enable DMA Request 8 7 ERQ7 Enable DMA Request 7 6 ERQ6 Enable DMA Request 6 5 ERQ5 Enable DMA Request 5 4 ERQ4 Enable DMA Request 4 3 ERQ3 Enable DMA Request 3 2 ERQ2 Enable DMA Request 2 0 1 0 1 0 1 0 1 0 1 0 1
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Memory map/register definition DMA_ERQ field descriptions (continued) Field Description 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 1 ERQ1 Enable DMA Request 1 0 ERQ0 Enable DMA Request 0 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_EEI field descriptions (continued) Field Description 13 EEI13 Enable Error Interrupt 13 12 EEI12 Enable Error Interrupt 12 11 EEI11 Enable Error Interrupt 11 10 EEI10 Enable Error Interrupt 10 9 EEI9 Enable Error Interrupt 9 8 EEI8 Enable Error Interrupt 8 7 EEI7 Enable Error Interrupt 7 6 EEI6 Enable Error Interrupt 6 5 EEI5 Enable Error Interrupt 5 4 EEI4 Enable Error Interrupt 4 3 EEI3 Enable Error Interrupt 3 2 EEI2 Enable E
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Memory map/register definition DMA_EEI field descriptions (continued) Field Description 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request 1 EEI1 Enable Error Interrupt 1 0 EEI0 Enable Error Interrupt 0 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error in
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests.
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Memory map/register definition The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_INT field descriptions (continued) Field Description 0 1 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active 10 INT10 Interrupt Request 10 9 INT9 Interrupt Request 9 8 INT8 Interrupt Request 8 7 INT7 Interrupt Request 7 6 INT6 Interrupt Request 6 5 INT5 Interrupt Request 5 4 INT4 Interrupt Request 4 3 INT3 Interrupt Request 3 2 INT2 Interrupt Request 2 1 INT1 Interrup
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Memory map/register definition 21.3.14 Error Register (DMA_ERR) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERR field descriptions (continued) Field Description 15 ERR15 Error In Channel 15 14 ERR14 Error In Channel 14 13 ERR13 Error In Channel 13 12 ERR12 Error In Channel 12 11 ERR11 Error In Channel 11 10 ERR10 Error In Channel 10 9 ERR9 Error In Channel 9 8 ERR8 Error In Channel 8 7 ERR7 Error In Channel 7 6 ERR6 Error In Channel 6 5 ERR5 Error In Channel 5 4 ERR4 Error In Channel 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Memory map/register definition DMA_ERR field descriptions (continued) Field Description 0 1 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred 3 ERR3 Error In Channel 3 2 ERR2 Error In Channel 2 1 ERR1 Error In Channel 1 0 ERR0 Error In Channel 0 0 1 0 1 0 1 0 1 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred An error in the corresponding channel has not occurred An error in the
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions Field 31–16 Reserved Description This read-only field is reserved and always has the value zero.
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Memory map/register definition DMA_HRS field descriptions (continued) Field Description 4 HRS4 Hardware Request Status Channel 4 3 HRS3 Hardware Request Status Channel 3 2 HRS2 Hardware Request Status Channel 2 1 HRS1 Hardware Request Status Channel 1 0 HRS0 Hardware Request Status Channel 0 0 1 0 1 0 1 0 1 0 1 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present A hardware service request for the corre
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_DCHPRIn field descriptions (continued) Field Description 0 1 6 DPA Channel n cannot be suspended by a higher priority channel’s service request Channel n can be temporarily suspended by the service request of a higher priority channel Disable Preempt Ability 0 1 5–4 Reserved Channel n can suspend a lower priority channel Channel n cannot suspend any channel, regardless of channel priority This read-only field is reserved and always has the value
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Memory map/register definition 21.3.18 TCD Signed Source Address Offset (DMA_TCD_SOFF) Addresses: 4000_8000h base + 1004h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 Read 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* SOFF Write Reset 7 x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_ATTR field descriptions (continued) Field Description 10–8 SSIZE Source data transfer size The attempted use of a Reserved encoding causes a configuration error. 000 001 010 011 100 101 110 111 8-bit 16-bit 32-bit Reserved 16-byte Reserved Reserved Reserved 7–3 DMOD Destination Address Modulo 2–0 DSIZE Destination Data Transfer Size See the SMOD definition See the SSIZE definition 21.3.
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Memory map/register definition DMA_TCDn_NBYTES_MLNO field descriptions (continued) Field Description is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued) Field Description As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted; although, it may be stalled by using the bandwidth control field, or via preemption.
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Memory map/register definition DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description 9–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_DADDR field descriptions Field Description 31–0 DADDR Destination Address Memory address pointing to the destination data. 21.3.25 TCD Signed Destination Address Offset (DMA_TCD_DOFF) Addresses: 4000_8000h base + 1014h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 Read 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* DOFF Write Reset x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions Field Description 15 ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKNO field descriptions Field Description 15 ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
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Memory map/register definition DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else • This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is reported. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. 7 DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated.
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Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field Description 0 1 1 INTMAJOR The half-point interrupt is disabled The half-point interrupt is enabled Enable an interrupt when major iteration count completes If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description 0 1 14–13 Reserved The channel-to-channel linking is disabled The channel-to-channel linking is enabled This read-only field is reserved and always has the value zero.
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Functional description DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) 64 eDMA Engine Program Model/ Channel Arbitration Read Data n-1 Internal Peripheral Bus To/From Crossbar Switch 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n.
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Functional description eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus 0 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-290.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 Internal Peripheral Bus 0 1 2 eDMA En g in e Program Model/ Channel Arbitration Read Data Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-291. eDMA operation, part 3 21.4.
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Functional description • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled.
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Chapter 21 Direct Memory Access Controller (eDMA) loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled.
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Functional description address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 21.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables.
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Chapter 21 Direct Memory Access Controller (eDMA) The eDMA design supports the following hardware service request sequence: Table 21-293. Hardware service request process, cycles 1–7 Cycle Description 1 eDMA peripheral request is asserted. 2 The eDMA peripheral request is registered locally in the eDMA module and qualified. TCDn_CSR[START] bit initiated requests start at this point with the registering of the user write to TCDn word 7. 3 Channel arbitration begins. 4 Channel arbitration completes.
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Functional description Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral busto-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle ? +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. Table 21-295.
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Chapter 21 Direct Memory Access Controller (eDMA) PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.
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Initialization/application information 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. 6.
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Chapter 21 Direct Memory Access Controller (eDMA) The following figure shows how each DMA request initiates one minor-loop transfer, or iteration, without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER).
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Initialization/application information 21.5.2 Programming errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). For all error types other than channel priority error, the channel number causing the error is recorded in the ES register.
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Chapter 21 Direct Memory Access Controller (eDMA) For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination.
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Initialization/application information h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop complete. 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. 21.5.4.
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Chapter 21 Direct Memory Access Controller (eDMA) f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0. 8. The channel retires → one iteration of the major loop.
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Initialization/application information 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 21.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2.
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Chapter 21 Direct Memory Access Controller (eDMA) complete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration.
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Initialization/application information DADDR, and NBYTES, decrements to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 21.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active.
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Chapter 21 Direct Memory Access Controller (eDMA) Because software can change the configuration during execution, a coherency sequence must be followed. Consider the scenario the user attempts to execute a dynamic channel link by enabling the TCDn_CSR[MAJOR_E_LINK] bit as the eDMA engine retires the channel. The TCDn_CSR[MAJOR_E_LINK] would be set in the programmer's model, but it would be indeterminate whether the actual link was made before the channel retired.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 490 Freescale Semiconductor, Inc.
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Chapter 22 External Watchdog Monitor (EWM) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
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Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles. • One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode.
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Chapter 22 External Watchdog Monitor (EWM) 22.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 22.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. 22.1.3 Block Diagram This figure shows the EWM block diagram.
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EWM Signal Descriptions 22.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal EWM_in EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 22.3 Memory Map/Register Definition This section contains the module memory map and registers.
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Chapter 22 External Watchdog Monitor (EWM) Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000h Bit 7 6 Read 5 4 3 0 Write Reset 0 0 0 0 0 2 1 0 INEN ASSIN EWMEN 0 0 0 EWM_CTRL field descriptions Field 7–3 Reserved 2 INEN 1 ASSIN 0 EWMEN Description This read-only field is reserved and always has the value zero. Input Enable. This bit when set, enables the EWM_in port. EWM_in's Assertion State Select. Default assert state of the EWM_in signal is logic zero.
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Memory Map/Register Definition 22.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error.
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Chapter 22 External Watchdog Monitor (EWM) EWM_CMPH field descriptions Field 7–0 COMPAREH Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required. 22.4 Functional Description The following sections describe functional details of the EWM module. 22.4.
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Functional Description Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 22.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit.
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Chapter 22 External Watchdog Monitor (EWM) The EWM compare registers are used to create a service window, which is used by the CPU to service/refresh the EWM module. • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. It is illegal to program CMPL and CMPH with same value.
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Functional Description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 500 Freescale Semiconductor, Inc.
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Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Some reasons for such failures are: run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation.
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Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits, resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. • Quick test—Small time-out value programmed for quick test. • Byte test—Individual bytes of timer tested one at a time. • Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational.
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Chapter 23 Watchdog Timer (WDOG) 23.
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Functional Overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period.
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Chapter 23 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to bother with frequently servicing the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as per need.
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Functional Overview Updates in the write–once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • the stop, wait, and debug mode enable bits • the standby mode enable bit • the IRQ_RST_EN bit The operations of refreshing the watchdog goes undetected during the WCT. 23.3.3 Refreshing the Watchdog A robust refreshing mechanism has been chosen for the watchdog.
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Chapter 23 Watchdog Timer (WDOG) non-time-out exception (see Generated Resets and Interrupts). You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 23.3.6 Low Power Modes of Operation • In Wait mode, if the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out. After reset the WDOG reset counter increments by one.
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Testing the Watchdog The entry into Debug mode within WCT time after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT time. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result. Upon exit from this mode, the WDOG timer restarts and the WDOG has to be unlocked and configured within WCT time. 23.
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Chapter 23 Watchdog Timer (WDOG) 23.4.2 Byte Test The byte test implements more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register.
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Backup Reset Generator Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts for more details. 23.5 Backup Reset Generator The backup reset generator generates the final reset which goes out to the system.
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Chapter 23 Watchdog Timer (WDOG) • A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. • A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant.
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Memory Map and Register Definition WDOG memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4005_200E Watchdog Unlock Register (WDOG_UNLOCK) 16 R/W D928h 23.7.8/ 516 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 16 R/W 0000h 23.7.9/ 517 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 16 R/W 0000h 23.7.10/ 517 4005_2014 Watchdog Reset Count Register (WDOG_RSTCNT) 16 R/W 0000h 23.7.
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Chapter 23 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description 0 1 10 TESTWDOG 9 Reserved 8 STNDBYEN Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
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Memory Map and Register Definition WDOG_STCTRLH field descriptions (continued) Field Description 0 1 WDOG is disabled. WDOG is enabled. 23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: WDOG_STCTRLL is 4005_2000h base + 2h offset = 4005_2002h Bit Write INTFLG Read 15 Reset 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 Reserved 0 0 0 0 0 0 0 0 WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag.
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Chapter 23 Watchdog Timer (WDOG) 23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain.
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Memory Map and Register Definition 23.7.6 Watchdog Window Register Low (WDOG_WINL) You must set the Window Register value lower than the Time-out Value Register.
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Chapter 23 Watchdog Timer (WDOG) WDOG_UNLOCK field descriptions Field Description 15–0 You can write the unlock sequence values to this register to make the watchdog write once registers WDOGUNLOCK writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens up a window equal in length to the WCT within which you can update the registers.
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Watchdog Operation with 8-bit access 23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT) Address: WDOG_RSTCNT is 4005_2000h base + 14h offset = 4005_2014h Bit 15 14 13 12 11 10 9 Read 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSTCNT Write Reset 8 0 0 0 0 0 0 0 0 0 WDOG_RSTCNT field descriptions Field Description 15–0 RSTCNT Counts the number of times the watchdog resets the system. This register is reset only on a POR.
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Chapter 23 Watchdog Timer (WDOG) 23.8.1 General Guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, you must try to place the two 8-bit accesses one after the other in your code. 23.8.
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Restrictions on Watchdog Operation takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged.
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Chapter 23 Watchdog Timer (WDOG) • The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. • You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock.
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Restrictions on Watchdog Operation K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 522 Freescale Semiconductor, Inc.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock.
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Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL) • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter • Can be used as a clock source for other on-chip peripherals.
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Chapter 24 Multipurpose Clock Generator (MCG) • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided • MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a
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Introduction Crystal Oscillator External Reference Clock CLKS ATMS OSCINIT PLLCLKEN EREFS IREFS HGO PLLS RANGE MCG Crystal Oscillator Enable Detect STOP IREFSTEN Auto Trim Machine IRCLKEN SCTRIM SCFTRIM FCTRIM Internal Reference Clock Generator MCGIRCLK IRCS CLKS Slow Clock Fast Clock IRCSCLK /2 MCGOUTCLK MCGFLLCLK CME DRS External Clock Monitor DMX32 Filter DCO PLLS DCOOUT FLL FRDIV / 2n n=0-7 MCGPLLCLK IREFS Clock Valid LP /2 / 25 Sync MCGFFCLK PRDIV LOLIE /(1,2,3,
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG Modes of Operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written to when in supervisor mode.
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Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000h Bit 7 Read 5 CLKS Write Reset 6 0 4 3 FRDIV 0 0 0 0 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 MCG_C1 field descriptions Field 7–6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5–3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 24.3.
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Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description 0 1 0 IRCS FLL (or PLL) is not disabled in bypass modes. FLL (or PLL) is disabled in bypass modes (lower power) Internal Reference Clock Select Selects between the fast or slow internal reference clock source. 0 1 Slow internal reference clock selected. Fast internal reference clock selected. 24.3.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.4 MCG Control 4 Register (MCG_C4) Reset values for DRST and DMX32 bits are 0. Address: MCG_C4 is 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: • x = Undefined at reset. • A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.
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Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description 10 11 4–1 FCTRIM Encoding 2 — Mid-high range. Encoding 3 — High range. Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). Increasing the binary value increases the period, and decreasing the value decreases the period.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description 0 1 5 PLLSTEN MCGPLLCLK is active. PLL Stop Enable Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 1 4–0 PRDIV MCGPLLCLK is inactive. MCGPLLCLK is disabled in any of the Stop modes.
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Memory Map/Register Definition 24.3.6 MCG Control 6 Register (MCG_C6) Address: MCG_C6 is 4006_4000h base + 5h offset = 4006_4005h Bit Read Write Reset 7 6 5 LOLIE PLLS CME 0 0 0 4 3 2 1 0 0 0 VDIV 0 0 0 MCG_C6 field descriptions Field 7 LOLIE Description Loss of Lock Interrrupt Enable Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS is set.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C6 field descriptions (continued) Field Description Table 24-9. PLL VCO Divide Factor (continued) 00001 25 01001 33 10001 41 11001 49 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 24.3.
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Memory Map/Register Definition MCG_S field descriptions (continued) Field Description While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV [4:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.8 MCG Auto Trim Control Register (MCG_ATC) Address: MCG_ATC is 4006_4000h base + 8h offset = 4006_4008h Bit Read Write Reset 7 6 ATME ATMS 0 0 5 4 3 ATMF 0 2 1 0 0 0 0 0 0 0 MCG_ATC field descriptions Field 7 ATME Description Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock.
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Functional Description MCG_ATCVH field descriptions Field 7–0 ATCVH Description ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.
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Chapter 24 Multipurpose Clock Generator (MCG) Reset FEI FEE FBI FBE BLPE BLPI PBE PEE Entered from any state when the MCU enters Stop mode Stop Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 24-12. MCG Mode State Diagram NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10.
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Functional Description Table 24-14. MCG Modes of Operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 1 • C6[PLLS] bit is written to 0 In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC).
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Chapter 24 Multipurpose Clock Generator (MCG) Table 24-14. MCG Modes of Operation (continued) Mode Description FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz.
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Functional Description Table 24-14. MCG Modes of Operation (continued) Mode Description Bypassed Low Power Internal (BLPI)1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 01 • C1[IREFS] bit is written to 1 • C6[PLLS] bit is written to 0 • C2[LP] bit is written to 1 In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.4.1.2 MCG Mode Switching The C1[IREFS] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the S[IREFST] bit. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. The C1[CLKS] bits can also be changed at anytime, but the actual switch to the newly selected clock is shown by the S[CLKST] bits.
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Functional Description selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.4.6 MCG PLL Clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, refer to the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK] is set. 24.4.
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Initialization / Application Information Before the ATM can be enabled, the ATM expected count needs to get derived and stored into the ATCV register.
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Chapter 24 Multipurpose Clock Generator (MCG) 2. Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source. • If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source.
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Initialization / Application Information • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.5.2 Using a 32.768 kHz Reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 Mhz at mid-low-range.
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Initialization / Application Information Table 24-15. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) (fint * F) Typical fMCGOUTCLK = 20 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) *F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) fext fext / FLL_R must be in the range of 31.25 kHz to 39.
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Chapter 24 Multipurpose Clock Generator (MCG) • C1[CLKS] set to 2'b10 in order to select external reference clock as system clock source • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT] is 1, indicating the crystal selected by C2[EREFS] has been initialized.. d.
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Initialization / Application Information e. PBE: Then loop until S[LOCK] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 in order to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, With PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
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Chapter 24 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C IN BLPE MODE ? (S[LP]=1) C1 = 0x90 NO YES C2 = 0x1C (S[LP]=0) NO CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? YES CHECK S[IREFST] = 0? NO YES NO CHECK S[LOCK] = 1? YES CHECK NO S[CLKST] = %10? NO YES C1 = 0x10 YES C5 = 0x01 (C5[VDIV] = 1) ENTER BLPE MODE ? CHECK S[CLKST] = %11? NO NO YES CONTINUE YES IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 24-13.
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Initialization / Application Information 24.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK Frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, PEE must transition to PBE mode: a.
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Chapter 24 Multipurpose Clock Generator (MCG) • C1[CLKS] set to 2'b01 in order to switch the system clock to the internal reference clock. • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c.
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Initialization / Application Information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? NO CHECK S[CLKST] = %10 ? YES C1 = 0x54 YES ENTER NO NO CHECK S[IREFST] = 0? BLPE MODE ? YES NO YES C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? NO C6 = 0x00 YES C2 = 0x02 IN BLPE MODE ? (C2[LP]=1) NO CONTINUE YES IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 24-14. Flowchart of PEE to BLPI Mode Transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE Mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, BLPI must transition to FBI mode.
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Initialization / Application Information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 =0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 =0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 24-15. Flowchart of BLPI to FEE Mode Transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev.
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Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.
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Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU.
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Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
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External Clock Connections OSC XTAL EXTAL VSS RF Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC XTAL EXTAL VSS Cx Cy RF Crystal or Resonator Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3 25.6 External Clock Connections In external clock mode, the pins can be connected as shown below.
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Chapter 25 Oscillator (OSC) OSC XTAL EXTAL VSS Clock Input I/O Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) 4006_5000 Width Access (in bits) Register name OSC Control Register (OSC_CR) 8 R/W Reset value Section/ page 00h 25.71.1/ 563 25.71.
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Functional Description OSC_CR field descriptions (continued) Field Description 0 1 6 Reserved 5 EREFSTEN This read-only field is reserved and always has the value zero. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. Configures the oscillator load. Disable the selection. Add 4 pF capacitor to the oscillator load.
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Chapter 25 Oscillator (OSC) 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section.
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Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter.
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Chapter 25 Oscillator (OSC) Table 25-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain fosc_lo (1 kHz) up to fosc_lo (32.
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Reset 25.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 25.8.2.
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Chapter 25 Oscillator (OSC) 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
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Interrupts K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 570 Freescale Semiconductor, Inc.
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Chapter 26 RTC Oscillator 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 26.1.
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RTC Signal Descriptions control Amplitude detector clk out for RTC EXTAL32 gm Rf XTAL32 C2 C1 PAD PAD Figure 26-1. RTC Oscillator Block Diagram 26.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 26-1. RTC Signal Descriptions Signal EXTAL32 XTAL32 Description I/O Oscillator Input I Oscillator Output O 26.2.
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Chapter 26 RTC Oscillator 26.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 VSS EXTAL32 Crystal or Resonator Figure 26-2. Crystal Connections 26.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. Refer to RTC_CR for more details. 26.
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Reset Overview 26.6 Reset Overview There is no reset state associated with the RTC oscillator. 26.7 Interrupts The RTC oscillator does not generate any interrupts. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 574 Freescale Semiconductor, Inc.
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Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. • buffers that can accelerate flash memory transfers. 27.1.1 Overview The Flash Memory Controller manages the interface between the device and the dualbank flash memory.
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Modes of operation • Interface between the device and the dual-bank flash memory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory. • For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access. • Crossbar master access protection for setting no access, read only access, write only access, or read/write access for each crossbar master.
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Chapter 27 Flash Memory Controller (FMC) NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. Table 27-2.
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Memory map and register descriptions FMC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh 27.4.1/ 583 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001Fh 27.4.2/ 586 4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR) 32 R/W 3002_001Fh 27.4.3/ 588 4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h 27.4.
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Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F144 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0000_0000h 27.4.6/ 592 4001_F148 Cache Tag Storage (FMC_TAGVDW2S2) 32 R/W 0000_0000h 27.4.6/ 592 4001_F14C Cache Tag Storage (FMC_TAGVDW2S3) 32 R/W 0000_0000h 27.4.6/ 592 4001_F150 Cache Tag Storage (FMC_TAGVDW2S4) 32 R/W 0000_0000h 27.4.
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Memory map and register descriptions FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F214 Cache Data Storage (lower word) (FMC_DATAW0S2L) 32 R/W 0000_0000h 27.4.9/ 595 4001_F218 Cache Data Storage (upper word) (FMC_DATAW0S3U) 32 R/W 0000_0000h 27.4.8/ 594 4001_F21C Cache Data Storage (lower word) (FMC_DATAW0S3L) 32 R/W 0000_0000h 27.4.
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Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 32 R/W 0000_0000h 27.4.11/ 597 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) 32 R/W 0000_0000h 27.4.10/ 596 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 32 R/W 0000_0000h 27.4.
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Memory map and register descriptions FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F2B4 Cache Data Storage (lower word) (FMC_DATAW2S6L) 32 R/W 0000_0000h 27.4.13/ 599 4001_F2B8 Cache Data Storage (upper word) (FMC_DATAW2S7U) 32 R/W 0000_0000h 27.4.12/ 598 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 32 R/W 0000_0000h 27.4.
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Chapter 27 Flash Memory Controller (FMC) 27.4.
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Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description 0 1 19 M3PFD Master 3 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 18 M2PFD These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field Description This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 01 10 11 9–8 M4AP[1:0] Master 4 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.
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Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description 10 11 Only write accesses may be performed by this master Both read and write accesses may be performed by this master 27.4.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. The bit setting definitions are for each bit in the field.
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Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description 2 B0DPE Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 1 1 B0IPE Do not prefetch in response to data references. Enable prefetches in response to data references. Bank 0 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFB1CR field descriptions (continued) Field Description This read-only field defines the number of wait states required to access the bank 1 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed.
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Memory map and register descriptions FMC_PFB1CR field descriptions (continued) Field Description 0 B1SEBE Bank 1 Single Entry Buffer Enable This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its operation is independent from bank 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 1 Single entry buffer is disabled. Single entry buffer is enabled. 27.4.
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Chapter 27 Flash Memory Controller (FMC) 27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 1.
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Memory map and register descriptions 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 2.
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Chapter 27 Flash Memory Controller (FMC) 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 3.
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Memory map and register descriptions 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 0.
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Chapter 27 Flash Memory Controller (FMC) 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 0.
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Memory map and register descriptions 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 1.
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Chapter 27 Flash Memory Controller (FMC) 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 1.
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Memory map and register descriptions 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 2.
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Chapter 27 Flash Memory Controller (FMC) 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 2.
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Memory map and register descriptions 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 3.
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Chapter 27 Flash Memory Controller (FMC) 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 3.
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Functional description • The cache is configured for least recently used (LRU) replacement for all four ways. • The cache is configured for data or instruction replacement. • The single-entry buffer is enabled. Though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases.
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Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter.
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Introduction states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 28.1.1 Features The FTFL module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 28.1.1.
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Chapter 28 Flash Memory Module (FTFL) 28.1.2 Block Diagram The block diagram of the FTFL module is shown in the following figure. Interrupt Register access Status registers Memory controller Program flash 0 Control registers To MCU's flash controller Program flash 1 Programming acceleration RAM Figure 28-1. FTFL Block Diagram 28.1.
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External Signal Description IFR — Nonvolatile information register found in each flash block, separate from the main memory array. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. NVM Normal Mode — An NVM mode that provides basic user access to FTFL resources.
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Chapter 28 Flash Memory Module (FTFL) 28.3 Memory Map and Registers This section describes the memory map and registers for the FTFL module. Data read from unimplemented memory space in the FTFL module is undefined. Writes to unimplemented or reserved memory space (registers) in the FTFL module are ignored. 28.3.
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Memory Map and Registers Address Range Size (Bytes) Field Description 0x00 – 0xBF 192 Reserved 0xC0 – 0xFF 64 Program Once Field 28.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times.
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Chapter 28 Flash Memory Module (FTFL) FTFL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_0004 Flash Common Command Object Registers (FTFL_FCCOB3) 8 R/W 00h 28.33.5/ 615 4002_0005 Flash Common Command Object Registers (FTFL_FCCOB2) 8 R/W 00h 28.33.5/ 615 4002_0006 Flash Common Command Object Registers (FTFL_FCCOB1) 8 R/W 00h 28.33.5/ 615 4002_0007 Flash Common Command Object Registers (FTFL_FCCOB0) 8 R/W 00h 28.
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Memory Map and Registers NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it).
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Chapter 28 Flash Memory Module (FTFL) FTFL_FSTAT field descriptions (continued) Field Description 3–1 Reserved This read-only field is reserved and always has the value zero. 0 MGSTAT0 Memory Controller Command Completion Status Flag The MGSTAT0 status flag is set if an error is detected during execution of an FTFL command or during the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other error flags in this register.
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Memory Map and Registers FTFL_FCNFG field descriptions (continued) Field Description This bit issues a request to the memory controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip Configuration details on how to request this command. The ERSAREQ bit sets when an erase all request is triggered external to the FTFL and CCIF is set (no command is currently being executed).
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Chapter 28 Flash Memory Module (FTFL) During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The Flash basis for the values is signified by X in the reset value. Address: FTFL_FSEC is 4002_0000h base + 2h offset = 4002_0002h Bit 7 Read 6 5 KEYEN 4 3 MEEN 2 1 FSLACC 0 SEC Write Reset x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Memory Map and Registers FTFL_FSEC field descriptions (continued) Field Description These bits define the security state of the MCU. In the secure state, the MCU limits access to FTFL module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the FTFL module is unsecured using backdoor key access, the SEC bits are forced to 10b.
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Chapter 28 Flash Memory Module (FTFL) 28.33.5 Flash Common Command Object Registers (FTFL_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB.
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Memory Map and Registers FTFL_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] A Data Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number.
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Chapter 28 Flash Memory Module (FTFL) Addresses: FTFL_FPROT3 is 4002_0000h base + 10h offset = 4002_0010h FTFL_FPROT2 is 4002_0000h base + 11h offset = 4002_0011h FTFL_FPROT1 is 4002_0000h base + 12h offset = 4002_0012h FTFL_FPROT0 is 4002_0000h base + 13h offset = 4002_0013h Bit 7 6 5 4 Read 2 1 0 x* x* x* x* PROT Write Reset 3 x* x* x* x* * Notes: • x = Undefined at reset.
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Flash Operation in Low-Power Modes 28.4.1 Program Flash Memory Swap For devices that only contain program flash memory: The user can configure the logical memory map of the program flash space such that either of the two physical program flash blocks can exist at relative address 0x0000. This swap feature enables the lower half of the logical program flash space to be operational while the upper half is being updated for future use.
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Chapter 28 Flash Memory Module (FTFL) CAUTION The MCU should never enter stop mode while any FTFL command is running (CCIF = 0). NOTE While the MCU is in very-low-power modes (VLPR, VLPW, VLPS), the FTFL module does not accept flash commands. 28.4.4 Functional Modes of Operation The FTFL module has two operating modes: NVM Normal and NVM Special. The operating mode affects the command set availability (see Table 28-25). Refer to the Chip Configuration details of this device for how to activate each mode.
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Flash Operation in Low-Power Modes 28.4.7 Flash Program and Erase All flash functions except read require the user to setup and launch an FTFL command through a series of peripheral bus writes. The user cannot initiate any further FTFL commands until notified that the current command has completed. The FTFL command structure and operation are detailed in FTFL Command Operations. 28.4.8 FTFL Command Operations FTFL command operations are typically used to modify flash memory contents.
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Chapter 28 Flash Memory Module (FTFL) The FSTAT register contains a blocking mechanism, which prevents a new command from launching (can't clear CCIF) if the previous command resulted in an access error (FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. 28.4.8.1.
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Flash Operation in Low-Power Modes START Read: FSTAT register FCCOB Availability Check no CCIF = ‘1’? Previous command complete? yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? Results from previous command yes Clear the old errors Write 0x30 to FSTAT register no Write to the FCCOB registers to load the required command parameter. More Parameters? yes no Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 28-24.
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Chapter 28 Flash Memory Module (FTFL) FCMD Command Program flash 0 Program flash 1 Function 0x03 Read Resource IFR IFR Read 4 bytes from program flash IFR or version ID. 0x06 Program Longword × × Program 4 bytes in a program flash block. 0x08 Erase Flash Block × × Erase a program flash block. An erase of any flash block is only possible when unprotected. 0x09 Erase Flash Sector × × Erase all bytes in a program flash sector.
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Flash Operation in Low-Power Modes 28.4.8.3 FTFL Commands by Mode The following table shows the FTFL commands that can be executed in each flash operating mode. Table 28-25.
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Chapter 28 Flash Memory Module (FTFL) 28.4.9 Margin Read Commands The Read-1s commands (Read 1s All Blocks, Read 1s Block, and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply non-standard read reference levels to the program flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read.
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Flash Operation in Low-Power Modes 28.4.10 FTFL Command Description This section describes all FTFL commands that can be launched by a command write sequence. The FTFL sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: • There is an unrecognized command code in the FCCOB FCMD field. • There is an error in a FCCOB field for the specific commands. Refer to the error handling table provided for each command.
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Chapter 28 Flash Memory Module (FTFL) Table 28-27. Read 1s Block Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 3 Flash address [7:0]1 in the flash block to be verified 4 Read-1 Margin Choice 1. Must be longword aligned (Flash address [1:0] = 00). After clearing CCIF to launch the Read 1s Block command, the FTFL sets the read margin for 1s according to Table 28-28 and then reads all locations within the selected program flash block. Table 28-28.
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Flash Operation in Low-Power Modes Table 28-30. Read 1s Section Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 6 Read-1 Margin Choice 1. Must be phrase aligned (Flash address [2:0] = 000). Upon clearing CCIF to launch the Read 1s Section command, the FTFL sets the read margin for 1s according to Table 28-31 and then reads all locations within the specified section of flash memory. If the FTFL fails to read all 1s (i.e.
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Chapter 28 Flash Memory Module (FTFL) Table 28-33. Program Check Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 4 Margin Choice 8 Byte 0 expected data 9 Byte 1 expected data A Byte 2 expected data B Byte 3 expected data 1. Must be longword aligned (Flash address [1:0] = 00).
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Flash Operation in Low-Power Modes 28.4.10.4 Read Resource Command The Read Resource command allows the user to read data from special-purpose memory resources located within the FTFL module. The special-purpose memory resources available include program flash IFR space and the Version ID field. Each resource is assigned a select code as shown in Table 28-37. Table 28-36.
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Chapter 28 Flash Memory Module (FTFL) Table 28-38. Read Resource Command Error Handling (continued) Error Condition Error Bit Flash address is out-of-range for the targeted resource. FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] 28.4.10.5 Program Longword Command The Program Longword command programs four previously-erased bytes in the program flash memory using an embedded algorithm. CAUTION A Flash memory location must be in the erased state before being programmed.
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Flash Operation in Low-Power Modes The supplied address must be longword aligned (flash address [1:0] = 00): • • • • Byte 0 data is written to the supplied address ('start'), Byte 1 data is programmed to byte address start+0b01, Byte 2 data is programmed to byte address start+0b10, and Byte 3 data is programmed to byte address start+0b11. Table 28-40.
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Chapter 28 Flash Memory Module (FTFL) Table 28-42. Erase Flash Block Command Error Handling (continued) Error Condition Error Bit Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Any area of the selected flash block is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 28.4.10.
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Flash Operation in Low-Power Modes 28.4.10.7.1 Suspending an Erase Flash Sector Operation To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash Configuration Field Description) when CCIF is clear and the CCOB command field holds the code for the Erase Flash Sector command. During the Erase Flash Sector operation (see Erase Flash Sector Command), the FTFL samples the state of the ERSSUSP bit at convenient points.
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Chapter 28 Flash Memory Module (FTFL) The following figure shows how to suspend and resume the Erase Flash Sector operation.
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Flash Operation in Low-Power Modes 28.4.10.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer (see Flash Sector Programming). The section program buffer is limited to the lower half of the RAM. Data written to the upper half of the RAM is ignored and may be overwritten during Program Section command execution.
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Chapter 28 Flash Memory Module (FTFL) After the Program Section operation completes, the CCIF flag is set. The contents of the section program buffer may be changed by the Program Section operation. Table 28-46.
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Flash Operation in Low-Power Modes After clearing CCIF to launch the Read 1s All Blocks command, the FTFL : • sets the read margin for 1s according to Table 28-48, • checks the contents of the program flash are in the erased state. If the FTFL confirms that these memory resources are erased, security is released by setting the FSEC[SEC] field to the unsecure state.
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Chapter 28 Flash Memory Module (FTFL) Table 28-50. Read Once Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Returned Values 4 Read Once byte 0 value 5 Read Once byte 1 value 6 Read Once byte 2 value 7 Read Once byte 3 value After clearing CCIF to launch the Read Once command, a 4-byte Read Once record is read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set after the Read Once operation completes.
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Flash Operation in Low-Power Modes Table 28-52. Program Once Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 7 Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the FTFL first verifies that the selected record is erased. If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly.
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Chapter 28 Flash Memory Module (FTFL) All Blocks operation. The security byte and all other contents of the flash configuration field (see Flash Configuration Field Description) are erased by the Erase All Blocks command. If the erase-verify fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation completes. Table 28-55.
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Flash Operation in Low-Power Modes Table 28-56.
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Chapter 28 Flash Memory Module (FTFL) Table 28-58.
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Flash Operation in Low-Power Modes • 0x04 (Progress Swap to COMPLETE State) - After verifying that the current swap state is UPDATE-ERASED and that the flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0x0000.
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Chapter 28 Flash Memory Module (FTFL) swap system is in the UPDATE or UPDATE-ERASED state. Once the swap system has been initialized, the Erase All Blocks command can be used to uninitialize the swap system. Table 28-59.
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Flash Operation in Low-Power Modes Block0 Active States Block1 Active States Uninitialized0 0xFFFF 0xFFFF Ready0 0xFFFF 0x0000 Reset 2 1 Complete1 0xFFFF 0x0000 4 Update0 0xFF00 0x0000 UpErs1 0xFFFF 0xFF00 Erase Erase UpErs0 0xFF00 0xFFFF Update1 0x0000 0xFF00 2 4 Complete0 0x0000 0xFFFF Reset Ready1 0x0000 0xFFFF Legend Swap State Indicator0 Indicator1 Swap Control Code Erase: ERSBLK or ERSSCR commands Reset: POR, VLLSx exit, warm/system reset Figure 28-26.
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Chapter 28 Flash Memory Module (FTFL) Table 28-60.
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Flash Operation in Low-Power Modes 28.4.10.14.1 Swap State Determination During the reset sequence, the state of the swap system is determined by evaluating the IFR Swap Field in the program flash 1 IFR and the swap indicators located in each of the program flash blocks at the swap indicator address stored in the IFR Swap Field. Table 28-61.
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Chapter 28 Flash Memory Module (FTFL) Table 28-63. FTFL Access Summary Operating Mode Chip Security State Unsecure NVM Normal NVM Special Secure Full command set Full command set Only the Erase All Blocks and Read 1s All Blocks commands. 28.4.11.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field.
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Flash Operation in Low-Power Modes An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command. A reset of the chip is the only method to re-enable the Verify Backdoor Access Key command when a comparison fails. After the backdoor keys have been correctly matched, the chip is unsecured by changing the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only.
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Chapter 29 External Bus Interface (FlexBus) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations. 29.1.
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Signal Descriptions 29.1.
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Chapter 29 External Bus Interface (FlexBus) Table 29-1. FlexBus Signal Summary Signal Description I/O In a non-multiplexed configuration, this is the address bus. O FB_D[31:0]/ FB_AD[31:0] In a non-multiplexed configuration, this is the data bus. In a multiplexed configuration this bus is the address/data bus, FB_AD[31:0]. In nonmultiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24]. I/O FB_CS[5:0] General purpose chip-selects.
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Signal Descriptions 29.2.2 Chip Selects (FB_CS[5 :0]) The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer address is within the device's address space, as defined in the base- and mask-address registers. The actual number of chip selects available depends upon the pin configuration. 29.2.
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Chapter 29 External Bus Interface (FlexBus) 29.2.7 Transfer Size (FB_TSIZ[1:0]) For memory accesses, these signals, along with FB_TBST, indicate the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. For misaligned transfers, FB_TSIZ[1:0] indicates the size of each transfer.
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Memory Map/Register Definition Note When burst (FB_TBST = 0), transfer size is 16 bytes (FB_TSIZ[1:0] = 11) and the address is misaligned within the 16-byte boundary, the external device must be able to wrap around the address. 29.2.9 Transfer Acknowledge (FB_TA) This input signal indicates the external data transfer is complete. When the processor recognizes FB_TA during a read cycle, it latches the data and then terminates the bus cycle.
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Chapter 29 External Bus Interface (FlexBus) Note You must set CSMR0[V] before the chip select registers take effect. A bus error occurs when writing to reserved register locations. FB memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_C000 Chip select address register (FB_CSAR0) 32 R/W 0000_0000h 29.3.1/ 658 4000_C004 Chip select mask register (FB_CSMR0) 32 R/W 0000_0000h 29.3.
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Memory Map/Register Definition FB memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_C040 Chip select mask register (FB_CSMR5) 32 R/W 0000_0000h 29.3.2/ 659 4000_C044 Chip select control register (FB_CSCR5) 32 R/W 0000_0000h 29.3.3/ 660 4000_C060 Chip select port multiplexing control register (FB_CSPMCR) 32 R/W 0000_0000h 29.3.4/ 663 29.3.
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Chapter 29 External Bus Interface (FlexBus) 29.3.2 Chip select mask register (FB_CSMRn) CSMRn registers specify the address mask and allowable access types for the respective chip-selects.
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Memory Map/Register Definition FB_CSMRn field descriptions (continued) Field Description Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chipselects do not assert until V bit is set (except for FB_CS0, which acts as the global chip-select). Reset clears each CSMRn[V]. NOTE: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V] is set. Afterward, FB_CS[5:0] functions as programmed. 0 1 Chip select invalid Chip select valid 29.3.
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Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description (CSCRn[WS]). If the SWSEN bit is cleared, the WS value is used for all burst transfers and this field is ignored. 25–24 Reserved 23 SWSEN 22 EXTS 21–20 ASET This read-only field is reserved and always has the value zero.
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Memory Map/Register Definition FB_CSCRn field descriptions (continued) Field Description The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If AA is reserved, FB_TA must be asserted by the external system regardless of the number of generated wait states. In that case, the external transfer acknowledge ends the cycle.
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Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description Specifies whether burst writes are used for memory associated with each FB_CSn. 0 1 2–0 Reserved Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
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Functional Description FB_CSPMCR field descriptions (continued) Field 23–20 GROUP3 Description FlexBus signal group 3 multiplex control Controls the multiplexing of the FB_CS5, FB_TSIZ1, and FB_BE_23_16 signals. 0000 0001 0010 Else 19–16 GROUP4 FlexBus signal group 4 multiplex control Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals.
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Chapter 29 External Bus Interface (FlexBus) • Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. • Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. 29.4.1.
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Functional Description No bit ordering is required when connecting address and data lines to the FB_AD bus. For example, a full 16-bit address/16-bit data device connects its addr[15:0] to FB_AD[16:1] and data[15:0] to FB_AD[31:16]. See Data Byte Alignment and Physical Connections for a graphical connection. 29.4.
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Chapter 29 External Bus Interface (FlexBus) Byte Select External Data Bus FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0] 32-Bit Port Memory Byte 3 Byte 2 Byte 1 Byte 0 16-Bit Port Memory Byte 1 Byte 0 Byte 3 Byte 2 8-Bit Port Memory Driven with address values Byte 0 Byte 1 Driven with address values Byte 2 Byte 3 Figure 29-23.
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Functional Description Table 29-27. FlexBus Multiplexed Operating Modes for CSCRn[BLS]=0 8-bit 16-bit 32-bit Port Size and Phase FB_AD [31:24] [23:16] [15:8] Address phase Address Data phase Data Address phase Address Data phase Data Address Address phase Data phase [7:0] Address Data Address Table 29-28.
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Chapter 29 External Bus Interface (FlexBus) 4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. 29.4.5.1 Data Transfer Cycle States An on-chip state machine controls the data-transfer operation in the device. The following figure shows the state-transition diagram for basic read and write cycles. S0 Next Cycle Wait States S3 S1 S2 Figure 29-25.
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Functional Description 29.4.6 FlexBus Timing Examples Note The timing diagrams throughout this section use signal names that may not be included on your particular device. Ignore these extraneous signals. Note Throughout this section: • FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus • FB_A[Y] indicates an address bus that can be 32, 24, or 16 bits wide. 29.4.6.1 Basic Read Bus Cycle During a read cycle, the MCU receives data from memory or a peripheral device.
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Chapter 29 External Bus Interface (FlexBus) Note FB_TA does not have to be driven by the external device for internally-terminated bus cycles. Note The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and another module.
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Functional Description External Memory/Peripheral FlexBus 1. Set FB_R/W to write. 2. Place address on the external address signals. 3. Assert transfer start. 1. Decode address. 1. Negate transfer start. 2. Assert FB_CSn. 3. Drive data. 1. Select the appropriate slave device. 1. FlexBus asserts internal FB_TA (auto acknowledge/internal termination). 2. Latch data on the external address signals. 2. Sample FB_TA low. 3. Assert FB_TA (external termination). 1. Start next cycle. 1.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-29. Basic Write-Bus Cycle 29.4.6.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. 29.4.6.3.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 01 Figure 29-30. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24]. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 674 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=01 Figure 29-31. Single Byte-Write Transfer 29.4.6.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States The following figure illustrates the basic word read transfer to a 16-bit device with no wait states. • The address is driven on the full FB_AD[31:8] bus in the first clock.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 10 Figure 29-32. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16]. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 676 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 29-33. Single Word-Write Transfer 29.4.6.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-34. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 678 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=00 Figure 29-35. Longword-Write Transfer 29.4.6.4 Timing Variations The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data. 29.4.6.4.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-36. Basic Read-Bus Cycle (No Wait States) K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 680 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-37. Basic Write-Bus Cycle (No Wait States) If wait states are used, the S1 state repeats continuously until the the chip-select autoacknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-38. Read-Bus Cycle (One Wait State) K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 682 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-39. Write-Bus Cycle (One Wait State) 29.4.6.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis.
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Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-40. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 684 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-41. Write-Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, a programmable address hold option for each chip select exists. Address and attributes can be held one to four clocks after chip-select, byteselects, and output-enable negate.
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Functional Description FB_CLK Address FB_A[Y] FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-42. Read Cycle with Two-Clock Address Hold (No Wait States) K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 686 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-43. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Functional Description FB_CLK FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-44. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 29.4.7 Burst Cycles The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination. The initiation of a burst cycle is encoded on the size pins.
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Chapter 29 External Bus Interface (FlexBus) Table 29-30. Transfer Size and Port Size Translation Burst-Inhibited: Number of Transfers Port Size PS[1:0] Transfer Size FB_TSIZ[1:0] 01 (8-bit) 10 (16-bits) 2 00 (32-bits) 4 11 (16 bytes) 16 00 (32 bits) 2 11 (16 bytes) 8 11 (line) 4 1x (16-bit) 00 (32-bit) Burst Enabled: Number of Beats The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying termination of the cycle can add wait states.
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Functional Description FB_CLK FB_A[Y] Add+1 Address FB_D[X] Address Data Add+2 Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 11 Figure 29-45. 32-bit-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States) The following figure shows a 32-bit write to an 8-bit device with burst enabled. The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24].
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Add+1 Data Add+2 Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-46. 32-bit-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States) The following figure shows a 32-bit read from an 8-bit device with burst inhibited. The transfer results in four individual transfers.
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Functional Description FB_CLK FB_A[Y] FB_D[X] Address Add Add+1 Data Add+1 Data Add+2 Add+2 Data Add+3 Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OE FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 00 TSIZ = 01 Figure 29-47. 32-bit-Read Burst-Inhibited from 8-Bit Port (No Wait States) The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The transfer results in four individual transfers.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Add Add+1 Data Add+1 Add+2 Data Add+2 Data Add+3 Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 01 TSIZ = 00 Figure 29-48. 32-bit-Write Burst-Inhibited to 8-Bit Port (No Wait States) The following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats.
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Functional Description FB_CLK FB_A[Y] FB_D[X] Address Address Data Add+1 Data Add+2 Data Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ = 00 Figure 29-49. 32-bit-Read Burst from 8-Bit Port 3-2-2-2 (One Wait State) The following figure illustrates a write burst transfer with one wait state. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 694 Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Add+1 Address Add+2 Data Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-50. 32-bit-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State) If address setup and hold are used, only the first and last beat of the burst cycle are affected. The following figure shows a read cycle with one clock of address setup and address hold.
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Functional Description FB_CLK FB_A[Y] FB_D[X] Add+1 Address Address Data Data Add+2 Data Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=11 Figure 29-51. 32-bit-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold) The following figure shows a write cycle with one clock of address setup and address hold.
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Chapter 29 External Bus Interface (FlexBus) 29.4.8 Extended Transfer Start/Address Latch Enable The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address and attributes are valid. By default, the FB_TS/FB_ALE signal asserts for a single bus clock cycle. When CSCRn[EXTS] is set, the FB_TS/FB_ALE signal asserts and remain asserted until the first positive clock edge after FB_CSn asserts. See the following figure.
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Initialization/Application Information The types of accesses that cause the access to terminate with a bus error are: • • • • • • Writes to write-protected region Address with no hit to any chip select Address with hits to multiple chip selects Writes to reserved addresses in the memory map Writes to reserved bits in the CSPMCR register FlexBus accesses when the FlexBus is secure Also, the device can hang if the FlexBus is configured for external termination and the CSPMCR is not configured for FB_TA.
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Chapter 30 EzPort 30.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. EzPort is a serial flash programming interface that allows In-System Programming (ISP) of flash memory contents on a 32 bit general purpose micro-controller. Memory contents can be read, erased and programmed from off-chip in a compatible format to many standalone flash memory chips, without necessitating the removal of the micro-controller from the system. 30.1.
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Overview EzPort Enabled G EZP_CS EZP_CK Flash Controller EzPort EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Micro-controller Core Figure 30-1. EzPort Block Diagram 30.1.2 Features The EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. • Able to read, erase and program flash memory. • Able to reset the micro-controller, allowing it to boot from the flash memory after the memory has been configured. 30.1.
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Chapter 30 EzPort The EzPort provides a simple interface to connect an external device to the flash memory on board a 32 bit micro-controller. The interface itself is compatible with the SPI interface (with the EzPort operating as a slave) running in either of the two following modes with data transmitted most significant bit first: • CPOL = 0, CPHA = 0 • CPOL = 1, CPHA = 1 Commands are issued by the external device to erase, program or read the contents of the flash memory.
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Command Definition 30.2.2 EzPort Chip Select (EZP_CS) Chip select for signalling the start and end of serial transfers. If EZP_CS is asserted during and when the micro-controller's reset out signal is negated, then EzPort is enabled out of reset; otherwise it is disabled. After EzPort is enabled, asserting EZP_CS commences a serial data transfer, which continues until EZP_CS is negated again.
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Chapter 30 EzPort Table 30-2. EzPort Commands (continued) Command Description Code Address Bytes Data Bytes Accepted when secure? RESET Reset Chip 0xB9 0 0 Yes WRFCCOB Write FCCOB Registers 0xBA 0 12 Yes6 FAST_RDFCCOB Read FCCOB registers at high speed 0xBB 0 1 - 122 No 1. 2. 3. 4. Address must be 32-bit aligned (two LSBs must be zero). One byte of dummy data must be shifted in before valid data is shifted out. Address must be 64-bit aligned (three LSBs must be zero).
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Command Definition Table 30-3. EzPort Status Register R 7 6 FS WEF 0/11 0 5 4 3 2 1 0 BEDIS WEN WIP 0/12 0 13 W Reset: 0 0 0 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects if bulk erase is enabled or disabled out of reset 3. Initial value of WIP is 1, but the value clears to 0 after EzPort initialization is complete Table 30-4. EzPort Status Register Field Descriptions Field Description 0 Write in progress.
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Chapter 30 EzPort 30.3.1.4 Read Data The Read Data (READ) command returns data from the flash memory . The initial address must be 32-bit aligned (the two LSBs must be zero). Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing. In this way, the entire contents of flash can be returned by one command.
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Command Definition This command is not accepted if the WEF, WIP, or FS bit is set or if the WEN bit is not set in the EzPort status register. 30.3.1.7 Sector Erase The Sector Erase (SE) command erases the contents of one sector of flash memory. The three byte address sent after the command byte can be any address within the sector to erase, but must be a 64-bit aligned address (the three LSBs must be zero).
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Chapter 30 EzPort NOTE The flash is configured in NVM special mode, restricting which commands can be executed by the flash when security is enabled. After receiving 12 bytes of data, EzPort writes the data to the FCCOB 0-B registers in the flash and then automatically launches the command within the flash. If greater or less than 12 bytes of data is received, this command has unexpected results and may result in the WEF flag being set.
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Flash Memory Map for EzPort Access K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 708 Freescale Semiconductor, Inc.
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Chapter 31 Cyclic redundancy check (CRC) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The 16/32-bit code is calculated for 32 bits of data at a time. 31.1.
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Memory map and register descriptions 31.1.2 Block diagram This is a block diagram of the CRC. TOT WAS FXOR TOTR Seed Reverse Logic MUX CRC Data Register [31:24] [23:16] [15:8] [7:0] NOT Logic CRC Data Reverse Logic Checksum CRC Polynomial Register [31:24] [23:16] [15:8] [7:0] CRC Data Register [31:24] [23:16] [15:8] [7:0] CRC Engine Data Combine Logic Polynomial 16-/32-bit Select TCRC Figure 31-1. Programmable cyclic redundancy check (CRC) block diagram 31.1.
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Chapter 31 Cyclic redundancy check (CRC) CRC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_2000 CRC Data Register (CRC_CRC) 32 R/W FFFF_ FFFFh 31.2.1/ 711 4003_2004 CRC Polynomial Register (CRC_GPOLY) 32 R/W 0000_1021h 31.2.2/ 712 4003_2008 CRC Control Register (CRC_CTRL) 32 R/W 0000_0000h 31.2.3/ 713 31.2.1 CRC Data Register (CRC_CRC) The CRC data register contains the value of the seed, data, and checksum.
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Memory map and register descriptions CRC_CRC field descriptions (continued) Field Description 23–16 HL CRC High Lower Byte 15–8 LU CRC Low Upper Byte 7–0 LL CRC Low Lower Byte In 16-bit CRC mode (the CTRL[TCRC] bit is 0), this field is not used for programming a seed value. In 32bit CRC mode (the CTRL[TCRC] bit is 1), values written to this field are part of the seed value when the CTRL[WAS] bit is 1.
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Chapter 31 Cyclic redundancy check (CRC) 31.2.3 CRC Control Register (CRC_CTRL) This register controls the configuration and working of the CRC module. Appropriate bits must be set before starting a new CRC calculation. A new CRC calculation is initialized by asserting the CTRL[WAS] bit and then writing the seed into the CRC data register.
PAGE 714
Functional description CRC_CTRL field descriptions (continued) Field 24 TCRC 23–0 Reserved Description Width of CRC protocol. 0 1 16-bit CRC protocol. 32-bit CRC protocol. This read-only field is reserved and always has the value zero. 31.3 Functional description 31.3.1 CRC initialization/re-initialization To enable the CRC calculation, the user must program the WAS, POLYNOMIAL, and necessary parameters for transpose and CRC result inversion in the applicable registers.
PAGE 715
Chapter 31 Cyclic redundancy check (CRC) 5. Write a 16-bit seed to CRC[LU:LL]. CRC[HU:HL] are not used. 6. Clear the CTRL[WAS] bit to start writing data values. 7. Write data values into CRC[HU:HL:LU:LL]. A CRC is computed on every data value write, and the intermediate CRC result is stored back into CRC[LU:LL]. 8. When all values have been written, read the final CRC result from CRC[LU:LL]. Transpose and complement operations are performed "on the fly" while reading or writing values.
PAGE 716
Functional description 31.3.3.1 Types of transpose The CRC module provides several types of transpose functions to flip the bits and/or bytes (for both writing input data and reading the CRC result, separately using the CTRL[TOT] or CTRL[TOTR] fields) according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register. 1. CTRL[TOT] or CTRL[TOTR] is 00 No transposition occurs. 2.
PAGE 717
Chapter 31 Cyclic redundancy check (CRC) 31 7 24 23 16 15 8 0 15 8 23 16 7 31 0 24 Figure 31-7. Transpose type 11 NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only.
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Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 718 Freescale Semiconductor, Inc.
PAGE 719
Chapter 32 Analog-to-Digital Converter (ADC) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, refer to the Power Management information for the device. 32.1.
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Introduction • Input clock selectable from up to four sources • Operation in low power modes for lower noise operation • Asynchronous clock source for lower noise operation with option to output the clock • Selectable hardware conversion trigger with hardware channel select • Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value • Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-
PAGE 721
Chapter 32 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion Trigger Control ADHWTSn ADHWT SC1n ADTRG Control Registers (SC2, CFG1, CFG2) Async Clock Gen A D IC L K A D IV ADLPC/ADHSC MODE ADLSMP/ADLSTS DIFF ADCO trig g e r c o m p le te AIEN ADACKEN COCO ADCH C o m p a re tru e 1 Interrupt MCU STOP AD23 TempP ADACK Clock Divide Bus Clock 2 ALTCLK abort transfer sample initialize PGA DADP0 DADP2 DADP3 AD4 convert Control Sequencer VREF_OUT ADCK A D V IN P PG, MG A
PAGE 722
ADC Signal Descriptions Table 32-1. ADC Signal Descriptions (continued) Signal DADM[3:0] Description I/O Differential analog channel inputs I Single-ended analog channel inputs I VREFSH Voltage reference select high I VREFSL Voltage reference select low I VDDA Analog power supply I VSSA Analog ground I AD[23:4] 32.2.1 Analog power (VDDA) The ADC analog portion uses VDDA as its power connection. In some packages, VDDA is connected internally to VDD.
PAGE 723
Chapter 32 Analog-to-Digital Converter (ADC) In some packages, VREFH is connected in the package to VDDA and VREFL to VSSA. If externally available, the positive reference(s) may be connected to the same potential as VDDA or may be driven by an external source to a level between the minimum Ref Voltage High and the VDDA potential (VREFH must never exceed VDDA). Connect the ground references to the same voltage potential as VSSA. 32.2.
PAGE 724
Register Definition ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B00C Configuration register 2 (ADC0_CFG2) 32 R/W 0000_0000h 32.3.3/ 731 4003_B010 ADC data result register (ADC0_RA) 32 R 0000_0000h 32.3.4/ 732 4003_B014 ADC data result register (ADC0_RB) 32 R 0000_0000h 32.3.4/ 732 4003_B018 Compare value registers (ADC0_CV1) 32 R/W 0000_0000h 32.3.
PAGE 725
Chapter 32 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B05C ADC minus-side general calibration value register (ADC0_CLM4) 32 R/W 0000_0200h 32.3.21/ 745 4003_B060 ADC minus-side general calibration value register (ADC0_CLM3) 32 R/W 0000_0100h 32.3.22/ 746 4003_B064 ADC minus-side general calibration value register (ADC0_CLM2) 32 R/W 0000_0080h 32.3.
PAGE 726
Register Definition ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400B_B03C ADC plus-side general calibration value register (ADC1_CLP4) 32 R/W 0000_0200h 32.3.13/ 740 400B_B040 ADC plus-side general calibration value register (ADC1_CLP3) 32 R/W 0000_0100h 32.3.14/ 741 400B_B044 ADC plus-side general calibration value register (ADC1_CLP2) 32 R/W 0000_0080h 32.3.
PAGE 727
Chapter 32 Analog-to-Digital Converter (ADC) Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion. In software trigger mode (ADTRG=0), writes to the SC1A register subsequently initiate a new conversion (if the ADCH bits are equal to a value other than all 1s). Similarly, writing any of the SC1n registers while that specific SC1n register is actively controlling a conversion aborts the current conversion.
PAGE 728
Register Definition ADCx_SC1n field descriptions (continued) Field 6 AIEN Description Interrupt enable AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted. 0 1 5 DIFF Differential mode enable DIFF configures the ADC to operate in differential mode. When enabled, this mode automatically selects from the differential channels, and changes the conversion algorithm and the number of cycles to complete a conversion.
PAGE 729
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 10111 11000 11001 11010 11011 11100 11101 11110 11111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. Reserved. Reserved. When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. Reserved.
PAGE 730
Register Definition ADCx_CFG1 field descriptions (continued) Field Description 0 1 6–5 ADIV Clock divide select ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK. 00 01 10 11 4 ADLSMP ADLSMP selects between different sample times based on the conversion mode selected. This bit adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs.
PAGE 731
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.3 Configuration register 2 (ADCx_CFG2) CFG2 register selects the special high speed configuration for very high speed conversions and selects the long sample time duration during long sample mode.
PAGE 732
Register Definition ADCx_CFG2 field descriptions (continued) Field Description ADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCK cycles added to the conversion time) to allow higher speed conversion clocks. 0 1 1–0 ADLSTS Normal conversion sequence selected. High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).
PAGE 733
Chapter 32 Analog-to-Digital Converter (ADC) Table 32-44.
PAGE 734
Register Definition The compare value 2 register (CV2) is utilized only when the compare range function is enabled (ACREN=1).
PAGE 735
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions Field 31–8 Reserved 7 ADACT Description This read-only field is reserved and always has the value zero. Conversion active ADACT indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 1 6 ADTRG Conversion trigger select ADTRG selects the type of trigger used for initiating a conversion.
PAGE 736
Register Definition ADCx_SC2 field descriptions (continued) Field Description 00 01 10 11 Default voltage reference pin pair (external pins VREFH and VREFL) Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. Reserved Reserved 32.3.
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Chapter 32 Analog-to-Digital Converter (ADC) ADCx_SC3 field descriptions (continued) Field Description 0 1 5–4 Reserved Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. This read-only field is reserved and always has the value zero. 3 ADCO Continuous conversion enable ADCO enables continuous conversions. 0 1 2 AVGE One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
PAGE 738
Register Definition ADCx_OFS field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 OFS Offset error correction value 32.3.9 ADC plus-side gain register (ADCx_PG) The plus-side gain register (PG) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode.
PAGE 739
Chapter 32 Analog-to-Digital Converter (ADC) Addresses: ADC0_MG is 4003_B000h base + 30h offset = 4003_B030h ADC1_MG is 400B_B000h base + 30h offset = 400B_B030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 MG W Reset 8 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 ADCx_MG field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has t
PAGE 740
Register Definition 32.3.12 ADC plus-side general calibration value register (ADCx_CLPS) For more information, refer to CLPD register description.
PAGE 741
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.14 ADC plus-side general calibration value register (ADCx_CLP3) For more information, refer to CLPD register description.
PAGE 742
Register Definition 32.3.16 ADC plus-side general calibration value register (ADCx_CLP1) For more information, refer to CLPD register description.
PAGE 743
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.
PAGE 744
Register Definition ADCx_PGA field descriptions (continued) Field Description 1000 1001 1010 1011 1100 1101 1110 1111 15–0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved This read-only field is reserved and always has the value zero. 32.3.19 ADC minus-side general calibration value register (ADCx_CLMD) CLMx contain calibration information that is generated by the calibration function.
PAGE 745
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.20 ADC minus-side general calibration value register (ADCx_CLMS) For more information, refer to CLMD register description.
PAGE 746
Register Definition 32.3.22 ADC minus-side general calibration value register (ADCx_CLM3) For more information, refer to CLMD register description.
PAGE 747
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.24 ADC minus-side general calibration value register (ADCx_CLM1) For more information, refer to CLMD register description.
PAGE 748
Functional description 32.4 Functional description The ADC module is disabled during reset, in low power stop mode (refer to the Power Management information for details), or when the ADCH bits in SC1n are all high. The module is idle when a conversion has completed and another conversion has not been initiated. When it is idle and the asynchronous clock output enable is disabled (ADACKEN is 0), the module is in its lowest power state.
PAGE 749
Chapter 32 Analog-to-Digital Converter (ADC) The PGA has only one voltage reference pair. The positive reference used is chip specific and depends on the MCU configuration. Refer to the Chip Configuration chapter on the PGA Voltage Reference specific to this MCU. The ground reference is the analog ground for the PGA. The ADC PGA register allows to control the PGA gain and modes of operation. 32.4.
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Functional description 32.4.3 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (VREFSH and VREFSL) used for conversions. Each pair contains a positive reference that must be between the minimum Ref Voltage High and VDDA, and a ground reference that must be at the same potential as VSSA. The two pairs are external (VREFH and VREFL) and alternate (VALTH and VALTL).
PAGE 751
Chapter 32 Analog-to-Digital Converter (ADC) When the conversion is completed, the result is placed in the data registers associated with the ADHWTSn received (ADHWTSA active selects RA register; ADHWTSn active selects Rn register). The conversion complete flag associated with the ADHWTSn received (the COCO bit in SC1n register) is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled (AIEN=1). 32.4.
PAGE 752
Functional description If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after SC1A register is written and continue until aborted. In hardware triggered operation (ADTRG=1 and one ADHWTSn event has occurred), continuous conversions begin after a hardware trigger event and continue until aborted.
PAGE 753
Chapter 32 Analog-to-Digital Converter (ADC) • The MCU is reset or enters Low Power Stop modes. • The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or Low Power Stop modes, RA and R n return to their reset states. 32.4.5.
PAGE 754
Functional description ADC Configuration 1 11 Sample time (ADCK cycles) 1 8 The total conversion time depends upon: the sample time (as determined by ADLSMP and ADLSTS bits), the MCU bus frequency, the conversion mode (as determined by MODE and SC1n[DIFF] bits), the high speed configuration (ADHSC bit), and the frequency of the conversion clock (fADCK). The ADHSC bit is used to configure a higher clock input frequency. This will allow faster overall conversion times.
PAGE 755
Chapter 32 Analog-to-Digital Converter (ADC) Table 32-108. Average number factor (AverageNum) AVGE AVGS[1:0] Average number factor (AverageNum) 0 xx 1 1 00 4 1 01 8 1 10 16 1 11 32 Table 32-109. Base Conversion Time (BCT) Mode Base conversion time (BCT) 8b s.e. 17 ADCK cycles 9b diff 27 ADCK cycles 10b s.e. 20 ADCK cycles 11b diff 30 ADCK cycles 12b s.e. 20 ADCK cycles 13b diff 30 ADCK cycles 16b s.e. 25 ADCK cycles 16b diff 34 ADCK cycles Table 32-110.
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Functional description 32.4.5.6 Conversion time examples The following examples use Figure 32-95 and the information provided in Table 32-107 through Table 32-111. 32.4.5.6.1 Typical conversion time configuration A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, long sample time disabled and high speed conversion disabled.
PAGE 757
Chapter 32 Analog-to-Digital Converter (ADC) Table 32-113. Typical conversion time (continued) Variable Time HSCAdder 0 The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting conversion time is 57.625 µs (AverageNum). This results in a total conversion time of 1.844 ms. 32.4.5.6.
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Functional description After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions has been completed. When hardware averaging is selected, the completion of a single conversion will not set the COCO bit.
PAGE 759
Chapter 32 Analog-to-Digital Converter (ADC) With the ADC range enable bit set, ACREN =1, and if compare value register 1 (CV1 value) is less than or equal to the compare value register 2 (CV2 value), then setting ACFGT will select a trigger-if-inside-compare-range inclusive-of-endpoints function. Clearing ACFGT will select a trigger-if-outside-compare-range, not-inclusive-ofendpoints function.
PAGE 760
Functional description for the different configurations. For best calibration results, it is recommended to set hardware averaging to maximum (AVGE=1, AVGS=11 for average of 32), ADC clock frequency fADCK less than or equal to 4 MHz, VREFH=VDDA, and to calibrate at nominal voltage and temperature. The input channel, conversion mode continuous function, compare function, resolution mode, and differential/single-ended mode are all ignored during the calibration function.
PAGE 761
Chapter 32 Analog-to-Digital Converter (ADC) stored in flash memory after an initial calibration and recovered prior to the first ADC conversion. This method should reduce the calibration latency to 20 register store operations on all subsequent power, reset, or Low Power Stop mode recoveries. 32.4.8 User defined offset function The ADC offset correction register (OFS) contains the user selected or calibration generated offset error correction value. This register is a 2’s complement, left justified.
PAGE 762
Functional description format and the effect will be an addition. An offset correction that results in an out-ofrange value will be forced to the minimum or maximum value (the minimum value for single-ended conversions is 0x0000; for a differential conversion it is 0x8000). To preserve accuracy, the calibrated offset value initially stored in the OFS register must be added to the user defined offset.
PAGE 763
Chapter 32 Analog-to-Digital Converter (ADC) 32.4.10 MCU wait mode operation Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters Wait mode, it continues until completion. Conversions can be initiated while the MCU is in Wait mode by means of the hardware trigger or if continuous conversions are enabled.
PAGE 764
Initialization information 32.4.11.2 Normal Stop mode with ADACK enabled If ADACK is selected as the conversion clock, the ADC continues operation during Normal Stop mode. Refer to the Chip Configuration chapter for configuration information for this MCU. If a conversion is in progress when the MCU enters Normal Stop mode, it continues until completion. Conversions can be initiated while the MCU is in Normal Stop mode by means of the hardware trigger or if continuous conversions are enabled.
PAGE 765
Chapter 32 Analog-to-Digital Converter (ADC) Note Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 32.5.1 ADC module initialization example This section provides details about the ADC module initialization. 32.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1.
PAGE 766
Initialization information CFG1 = 0x98 (%10011000) Bit 7 ADLPC 1 Bit 6:5 ADIV 00 Bit 4 ADLSMP 1 Bit 3:2 MODE 10 bit conversion. Bit 1:0 ADICLK 00 Configures for low power (lowers maximum clock speed. Sets the ADCK to the input clock ÷ 1. Configures for long sample time. Selects the single-ended 10-bit conversion, differential 11Selects the bus clock. SC2 = 0x00 (%00000000) Bit Bit Bit Bit Bit Bit Bit and VREFL).
PAGE 767
Chapter 32 Analog-to-Digital Converter (ADC) Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check No SC1n[COCO]=1? Yes Read Rn to clear SC1n[COCO] bit Continue Figure 32-97. Initialization Flowchart for Example 32.6 Application information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC. 32.6.
PAGE 768
Application information supply pins. In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDA and VSSA must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package.
PAGE 769
Chapter 32 Analog-to-Digital Converter (ADC) frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum (parasitic only). 32.6.1.3 Analog input pins The external analog inputs are typically shared with digital I/O pins on MCU devices.
PAGE 770
Application information SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2N) LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP and changing the ADLSTS bits (to increase the sample window) or decreasing ADCK frequency to increase sample time. 32.6.2.
PAGE 771
Chapter 32 Analog-to-Digital Converter (ADC) • For software triggered conversions, immediately follow the write to the SC1 register with a wait instruction or stop instruction. • For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces VDD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion.
PAGE 772
Application information For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB. 32.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers should be aware of them because they affect overall accuracy.
PAGE 773
Chapter 32 Analog-to-Digital Converter (ADC) This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes.
PAGE 774
Application information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 774 Freescale Semiconductor, Inc.
PAGE 775
Chapter 33 Comparator (CMP) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Comparator module (CMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from eight channels. One signal provided by the 6-bit DAC.
PAGE 776
6-bit DAC Key Features • Selectable interrupt on rising edge, falling edge, or both rising or falling edges of comparator output • Selectable inversion on comparator output • Comparator output may be: • Sampled • Windowed (ideal for certain PWM zero-crossing-detection applications) • Digitally Filtered • Filter can be bypassed • Can be clocked via external SAMPLE signal or scaled bus clock • External hysteresis can be used at the same time that the output filter is used for internal functions.
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Chapter 33 Comparator (CMP) 33.4 ANMUX Key Features • Two 8 to 1 channel mux • Operates the entire supply range 33.5 CMP, DAC, and ANMUX Diagram The following figure shows the block diagram for the High Speed Comparator, Digital to Analog Converter, and Analog MUX modules. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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CMP Block Diagram VRSEL Vin1 Vin2 VOSEL[5:0] MUX DAC output MUX 64-level DACEN DAC PSEL[2:0] CMP MUX Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP Sample Input CMP MUX ANMUX Window and Filter control INM IRQ CMPO MSEL[2:0] Figure 33-1. CMP, DAC and ANMUX Blocks Diagram 33.6 CMP Block Diagram The following figure shows the block diagram for the Comparator module. K20 Sub-Family Reference Manual, Rev.
PAGE 779
Chapter 33 Comparator (CMP) INTERNAL BUS FILT_PER EN,PMODE,HYSCTRL[1:0] COS INV OPE WE FILTER_CNT SE COUT IER/F CFR/F INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock Prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 33-2.
PAGE 780
Memory Map/Register Definitions • If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on COUT due to the fact that COUT (which is crossing clock domain boundaries) must be resynchronized to the bus clock. • CR1[WE] and CR1[SE] are mutually exclusive. 33.7 Memory Map/Register Definitions CMP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 33.7.
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Chapter 33 Comparator (CMP) CMP memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_3012 CMP Filter Period Register (CMP2_FPR) 8 R/W 00h 33.7.3/ 783 4007_3013 CMP Status and Control Register (CMP2_SCR) 8 R/W 00h 33.7.4/ 784 4007_3014 DAC Control Register (CMP2_DACCR) 8 R/W 00h 33.7.5/ 785 4007_3015 MUX Control Register (CMP2_MUXCR) 8 R/W 00h 33.7.6/ 786 1 0 33.7.
PAGE 782
Memory Map/Register Definitions CMPx_CR0 field descriptions (continued) Field Description 2 Reserved This read-only field is reserved and always has the value zero. 1–0 HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level. The hysteresis values associated with each level is devicespecific. See the device's data sheet for the exact values. 00 01 10 11 Level 0 Level 1 Level 2 Level 3 33.7.
PAGE 783
Chapter 33 Comparator (CMP) CMPx_CR1 field descriptions (continued) Field Description Refer to the device data sheet's CMP electrical specifications table for details on the impact of the modes below. 0 1 3 INV Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
PAGE 784
Memory Map/Register Definitions CMPx_FPR field descriptions Field 7–0 FILT_PER Description Filter Sample Period When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the Functional Description. This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to determine the sampling period. 33.7.
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Chapter 33 Comparator (CMP) CMPx_SCR field descriptions (continued) Field Description 0 1 3 IEF Interrupt disabled. Interrupt enabled. Comparator Interrupt Enable Falling The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted when the CFF bit is set. 0 1 2 CFR Interrupt disabled. Interrupt enabled. Analog Comparator Flag Rising During normal operation, the CFR bit is set when a rising edge on COUT has been detected.
PAGE 786
Memory Map/Register Definitions CMPx_DACCR field descriptions Field 7 DACEN Description DAC Enable This bit is used to enable the DAC. When the DAC is disabled, it is powered down to conserve power. 0 1 6 VRSEL 5–0 VOSEL DAC is disabled. DAC is enabled. Supply Voltage Reference Source Select 0 1 Vin1 is selected as resistor ladder network supply reference Vin. Vin2 is selected as resistor ladder network supply reference Vin.
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Chapter 33 Comparator (CMP) CMPx_MUXCR field descriptions (continued) Field 5–3 PSEL Description Plus Input MUX Control Determines which input is selected for the plus input of the comparator. For INx inputs, refer to CMP, DAC and ANMUX Blocks Diagram. NOTE: When an inappropriate operation selects the same input for both MUXes, the comparator automatically shuts down to prevent itself from becoming a noise generator.
PAGE 788
CMP Functional Description 33.8.1 CMP Functional Modes There are three main sub-blocks to the comparator module: the comparator itself, the window function and the filter function. The filter, CR0[FILTER_CNT] can be clocked from an internally or external clock source. Additionally, the filter is programmable with respect to how many samples must agree before a change on the output is registered. In the simplest case, only 1 sample must agree. In this case, the filter acts as a simple sampler.
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Chapter 33 Comparator (CMP) Table 33-29. Comparator Sample/Filter Controls (continued) Mode # CR1[EN] CR1[WE] CR1[SE] CR0[FILTER_C NT] FPR[FILT_PER] Operation 6 1 1 0 0x01 0x01 - 0xFF Windowed/Resampled mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT. Refer to the Windowed/Resampled Mode (# 6).
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CMP Functional Description 33.8.1.2 Continuous Mode (#s 2A & 2B) INTERNAL BUS EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT IER/F CFR/F 0 INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 33-27.
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Chapter 33 Comparator (CMP) 33.8.1.3 Sampled, Non-Filtered Mode (#s 3A & 3B) INTERNAL BUS EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 0 IER/F CFR/F 1 INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 33-28.
PAGE 792
CMP Functional Description INTERNAL BUS EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0 IER/F CFR/F 0 0x01 INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 33-29. Sampled, Non-Filtered (# 3B): Sampling interval internally derived 33.8.1.
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Chapter 33 Comparator (CMP) INTERNAL BUS EN, PMODE, HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT > 0x01 0 INP + - CMPO Polarity Select Window Control IER/F CFR/F 1 Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 33-30. Sampled, Filtered (# 4A): Sampling point externally driven K20 Sub-Family Reference Manual, Rev.
PAGE 794
CMP Functional Description INTERNAL BUS OPE FILT_PER EN, PMODE,HYSTCTR[1:0] COS INV WE FILTER_CNT SE COUT IER/F CFR/F >0x01 0 1 INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block INM IRQ COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 33-31.
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Chapter 33 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 33-32. Windowed Mode Operation INTERNAL BUS EN, PMODE,HYSCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 IER/F CFR/F 0 INP + - CMPO Polarity Select Window Control Interrupt Control Filter Block IRQ INM COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock FILT_PER Clock Prescaler 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 33-33.
PAGE 796
CMP Functional Description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 33.8.1.6 Windowed/Resampled Mode (# 6) The following figure uses the same input stimulus shown in Figure 33-32, and adds resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows. Again, prop delays and latency is ignored for clarity's sake.
PAGE 797
Chapter 33 Comparator (CMP) 33.8.1.7 Windowed/Filtered Mode (#7) This is the most complex mode of operation for the comparator block, as it utilizes both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] X FPR[FILT_PER]) + 1) X bus clock for the filter function. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1.
PAGE 798
CMP Functional Description 33.8.2.2 Stop Mode Operation Subject to platform-specific clock restrictions, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
PAGE 799
Chapter 33 Comparator (CMP) 33.8.4 Low Pass Filter The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT. Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system. Synchronization and edge detection are always used to determine status register bit values. They also apply to COUT for all sampling and windowed modes.
PAGE 800
CMP Functional Description If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when CR0[FILTER_CNT] consecutive samples all agree that the output value has changed. 33.8.4.2 Latency Issues The FPR[FILT_PER] value (or SAMPLE period) should be set such that the sampling period is just larger than the period of the expected noise. This way a noise spike will only corrupt one sample.
PAGE 801
Chapter 33 Comparator (CMP) Table 33-30. Comparator Sample/Filter Maximum Latencies (continued) Mode # CR1[ EN] CR1[ WE] CR1[ SE] CR0[FILTER _CNT] FPR[FILT_P ER] Operation Maximum Latency1 7 1 1 0 > 0x01 0x01 - 0xFF Windowed / Filtered mode TPD + (CR0[FILTER_CNT] x FPR[FILT_PER] x Tper) + 2Tper 1. TPD represents the intrinsic delay of the analog component plus the polarity select logic. TSAMPLE is the clock period of the external sample clock. Tper is the period of the bus clock. 33.
PAGE 802
DAC Functional Description Vin1 Vin2 MUX VRSEL VOSEL[5:0] DACEN Vin MUX DACO Figure 33-36. 6-bit DAC Block Diagram 33.12 DAC Functional Description This section provides DAC functional description. 33.12.1 Voltage Reference Source Select • Vin1 should be used to connect to the primary voltage source as supply reference of 64 tap resistor ladder • Vin2 should be used to connect to alternate voltage source (or primary source if alternate voltage source is not available) 33.
PAGE 803
Chapter 33 Comparator (CMP) 33.15 DAC Interrupts This module has no interrupts. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
PAGE 804
DAC Interrupts K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 804 Freescale Semiconductor, Inc.
PAGE 805
Chapter 34 12-bit Digital-to-Analog Converter (DAC) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 12-bit digital-to-analog converter (DAC) is a low power general purpose DAC. The output of this DAC can be placed on an external pin or set as one of the inputs to the analog comparator, Op-Amps, ADC, or other peripherals. 34.
PAGE 806
Memory Map/Register Definition DACREF_1 DACREF_2 DACRFS MUX AMP Buffer Vin DACEN MUX 4096-level VDD - LPEN Vo Vout + DACDAT[11:0] 12 Hardware Trigger DACBFWMF DACBWIEN DACSWTRG DACBFWM DACBFEN DACBFUP DACBFRP DATA BUFFER & DACBFRPTF DACBTIEN & OR dac_interrupt DACBFRPBF DACBBIEN & DACBFMD DACTRGSE Figure 34-1. DAC Block Diagram 34.
PAGE 807
Chapter 34 12-bit Digital-to-Analog Converter (DAC) DAC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400C_C000 DAC Data Low Register (DAC0_DAT0L) 8 R/W 00h 34.4.1/ 808 400C_C001 DAC Data High Register (DAC0_DAT0H) 8 R/W 00h 34.4.2/ 809 400C_C002 DAC Data Low Register (DAC0_DAT1L) 8 R/W 00h 34.4.1/ 808 400C_C003 DAC Data High Register (DAC0_DAT1H) 8 R/W 00h 34.4.
PAGE 808
Memory Map/Register Definition DAC memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 400C_C014 DAC Data Low Register (DAC0_DAT10L) 8 R/W 00h 34.4.1/ 808 400C_C015 DAC Data High Register (DAC0_DAT10H) 8 R/W 00h 34.4.2/ 809 400C_C016 DAC Data Low Register (DAC0_DAT11L) 8 R/W 00h 34.4.1/ 808 400C_C017 DAC Data High Register (DAC0_DAT11H) 8 R/W 00h 34.4.2/ 809 400C_C018 DAC Data Low Register (DAC0_DAT12L) 8 R/W 00h 34.
PAGE 809
Chapter 34 12-bit Digital-to-Analog Converter (DAC) DACx_DATnL field descriptions Field 7–0 DATA[7:0] Description When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. Vout = Vin * (1 + DACDAT0[11:0])/4096 When the DAC Buffer is enabled, DATA is mapped to the 16-word buffer. 34.4.
PAGE 810
Memory Map/Register Definition DACx_SR field descriptions (continued) Field Description 2 DACBFWMF DAC buffer watermark flag 1 DACBFRPTF DAC buffer read pointer top position flag 0 DACBFRPBF DAC buffer read pointer bottom position flag 0 1 0 1 0 1 The DAC buffer read pointer has not reached the watermark level. The DAC buffer read pointer has reached the watermark level. The DAC buffer read pointer is not zero. The DAC buffer read pointer is zero.
PAGE 811
Chapter 34 12-bit Digital-to-Analog Converter (DAC) DACx_C0 field descriptions (continued) Field 3 LPEN Description DAC low power control Refer to the device data sheet's 12-bit DAC electrical characteristics for details on the impact of the modes below. 0 1 high power mode. low power mode.
PAGE 812
Functional Description DACx_C1 field descriptions (continued) Field Description 01 10 11 2 words 3 words 4 words 2–1 DACBFMD DAC buffer work mode select 0 DACBFEN DAC buffer enable 00 01 10 11 0 1 Normal Mode Swing Mode One-Time Scan Mode Reserved Buffer read pointer disabled. The converted data is always the first word of the buffer. Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. 34.4.
PAGE 813
Chapter 34 12-bit Digital-to-Analog Converter (DAC) 34.5.1 DAC Data Buffer Operation When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage. When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word in the event the hardware trigger or the software trigger occurs.
PAGE 814
Functional Description 34.5.1.4 Buffer One-time Scan Mode The read pointer increases by one every time when the trigger occurs. When it reaches the upper limit, it stops at there. If read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop at there again. Note If the software set the read pointer to the upper limit, the read pointer will not advance in this mode. 34.5.2 DMA Operation When DMA is enabled, interrupt requests are not generated.
PAGE 815
Chapter 34 12-bit Digital-to-Analog Converter (DAC) NOTE The assignment of module modes to core modes is chipspecific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
PAGE 816
Functional Description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 816 Freescale Semiconductor, Inc.
PAGE 817
Chapter 35 Voltage Reference (VREFV1) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The VREFV1 Voltage Reference is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREFV1 can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
PAGE 818
Introduction 1.75 V Regulator SC[VREFST] 1.75 V 6 BITS TRM DEDICATED OUTPUT PIN BANDGAP VDDA SC[VREFEN] SC[MODE_LV] VREF_OUT 2 BITS 100nF REGULATION BUFFER VSSA Figure 35-1. Voltage reference block diagram 35.1.1 Overview The Voltage Reference provides a buffered reference voltage with high output current for use as an external reference. In addition, the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs.
PAGE 819
Chapter 35 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Tight-regulation buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT • Load regulation in tight-regulation mode 35.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait (VLPW) and Very Low Power Stop (VLPS).
PAGE 820
Memory Map and Register Definition VREF memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_4000 VREF Trim Register (VREF_TRM) 8 R/W Undefined 35.2.1/ 820 4007_4001 VREF Status and Control Register (VREF_SC) 8 R/W 00h 35.2.2/ 821 35.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference.
PAGE 821
Chapter 35 Voltage Reference (VREFV1) 35.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the VREF mode to be used.
PAGE 822
Functional Description VREF_SC field descriptions (continued) Field Description 10 11 Tight-regulation buffer enabled Reserved 35.3 Functional Description The Voltage Reference is a bandgap buffer system. Unity gain amplifiers are used. The VREF_OUT signal is available as an internal reference when it is enabled. A 100 nF capacitor must be connected between VREF_OUT and VSSA. The following table shows all possible function configurations of the Voltage Reference. Table 35-5.
PAGE 823
Chapter 35 Voltage Reference (VREFV1) 35.3.2.1 SC[MODE_LV]=00 The internal bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time for startup and stabilization. SC[VREFST] can be monitored to determine if the stabilization and startup is complete. The output buffer is disabled in this mode, and there is no buffered voltage output. The Voltage Reference is in standby mode.
PAGE 824
Initialization/Application Information When the Voltage Reference is already enabled and stabilized, changing SC[MODE_LV] will not clear SC[VREFST] but there will be some startup time before the output voltage at the VREF_OUT pin has settled. This is the buffer start up delay (Tstup) and the value is specified in the appropriate device data sheet. Also, there will be some settling time when a step change of the load current is applied to the VREF_OUT pin. When the 1.
PAGE 825
Chapter 36 Programmable Delay Block (PDB) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The programmable delay block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved.
PAGE 826
Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support • Up to eight DAC interval triggers • One interval trigger output per DAC • One 16-bit delay interval register per DAC trigger output • Optional bypass the delay interval trigger registers • Optional external triggers • Up to eight pulse ou
PAGE 827
Chapter 36 Programmable Delay Block (PDB) • Y — Total number of Pulse-Out's. • y — Pulse-Out number, valid value is 0 to Y-1. NOTE The number of module output triggers to core are chip-specific. For module to core output triggers implementation, refer to the Chip Configuration information. 36.1.3 Back-to-back Acknowledgement Connections PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, refer to the Chip Configuration information. 36.1.
PAGE 828
Introduction Ack 0 PDBCHnDLY0 = Pre-trigger 0 BB[0], TOS[0] Ch n pre-trigger 0 EN[0] Ack m PDBCHnDLYm = Pre-trigger m BB[m], TOS[m] Ch n pre-trigger m EN[m] Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD PDBCNT = PDB Counter Control Logic DACINTx CONT DAC interval trigger x = DAC Interval Counter x TOEx MULT EXTx DAC ext trigger input x PRESCALER DAC interval trigger x Trigger-In 0 Trigger-In 1 POyDLY1 Trigger-In 14 = SWTRIG POyDLY2 TRIGSEL Pulse Generation = P
PAGE 829
Chapter 36 Programmable Delay Block (PDB) 36.1.6 Modes of Operation PDB ADC trigger operates in the following modes. Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in backto-back operation of Bypass mode. Debug: Counter is paused when processor is in debug mode, the counter for dac trigger also paused in Debug mode.
PAGE 830
Memory Map and Register Definition PDB memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h 36.3.1/ 831 4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh 36.3.2/ 833 4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h 36.3.3/ 834 4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh 36.3.
PAGE 831
Chapter 36 Programmable Delay Block (PDB) 36.3.
PAGE 832
Memory Map and Register Definition PDBx_SC field descriptions (continued) Field 15 DMAEN Description DMA Enable When DMA is enabled, the PDBIF flag generates a DMA request instead of an interrupt. 0 1 14–12 PRESCALER DMA disabled DMA enabled Prescaler Divider Select 000 001 010 Counting uses the peripheral clock divided by multiplication factor selected by MULT. Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
PAGE 833
Chapter 36 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description This bit is set when the counter value is equal to the IDLY register. Writing zero clears this bit. 5 PDBIE PDB Interrupt Enable. This bit enables the PDB interrupt. When this bit is set and DMAEN is cleared, PDBIF generates a PDB interrupt. 0 1 4 Reserved PDB interrupt disabled PDB interrupt enabled This read-only field is reserved and always has the value zero.
PAGE 834
Memory Map and Register Definition PDBx_MOD field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 MOD PDB Modulus. These bits specify the period of the counter. When the counter reaches this value, it will be reset back to zero. If the PDB is in Continuous mode, the count begins anew. Reading these bits returns the value of internal register that is effective for the current cycle of PDB. 36.3.
PAGE 835
Chapter 36 Programmable Delay Block (PDB) PDBx_IDLY field descriptions (continued) Field Description These bits specify the delay value to schedule the PDB interrupt. It can be used to schedule an independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is equal to the IDLY. Reading these bits returns the value of internal register that is effective for the current cycle of the PDB. 36.3.
PAGE 836
Memory Map and Register Definition PDBx_CHnC1 field descriptions (continued) Field Description These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this MCU. 0 1 PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. 36.3.
PAGE 837
Chapter 36 Programmable Delay Block (PDB) 36.3.
PAGE 838
Memory Map and Register Definition 36.3.
PAGE 839
Chapter 36 Programmable Delay Block (PDB) PDBx_DACINTn field descriptions (continued) Field Description 15–0 INT DAC Interval These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal register that is effective for the current PDB cycle. 36.3.
PAGE 840
Functional Description PDBx_POnDLY field descriptions (continued) Field Description These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is equal to the DLY1. Reading these bits returns the value of internal register that is effective for the current PDB cycle. 15–0 DLY2 PDB Pulse-Out Delay 2 These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to the DLY2.
PAGE 841
Chapter 36 Programmable Delay Block (PDB) Trigger input event Ch n pre-trigger 0 Ch n pre-trigger 1 ... ... ... ... Ch n pre-trigger M Ch n trigger Figure 36-54. Pre-trigger and Trigger Outputs The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is cleared. In this case, when the trigger input event occurs, the pre-trigger m is asserted after two peripheral clock cycles. The PDB can be configured in back-to-back (B2B) operation.
PAGE 842
Functional Description 36.4.2 PDB Trigger Input Source Selection The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are connected to on-chip or off-chip event sources. The PDB can be triggered by software through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or software trigger. For the trigger input sources implemented in this MCU, refer to Chip Configuration information. 36.4.
PAGE 843
Chapter 36 Programmable Delay Block (PDB) MOD, IDLY CHnDLY1 CHnDLY0 DACINTx x3 DACINTx x2 PDB counter DACINTx 0 Trigger input event ... ... DAC internal trigger x ... ... Ch n pre-trigger 0 Ch n pre-trigger 1 Ch n trigger PDB interrupt Figure 36-55. PDB ADC Triggers and DAC Interval Triggers Use Case NOTE Because the DAC interval counters share the prescaler with PDB counter, PDB must be enabled if the DAC interval trigger outputs are used in the applications. 36.4.
PAGE 844
Functional Description • PDB Modulus Register (MOD) • PDB Interrupt Delay Register (IDLY) • PDB Channel n Delay m Register (CHnDLYm) • DAC Interval x Register (DACINTx) • PDB Pulse-Out y Delay Register (POyDLY) The internal registers of them are buffered and any values written to them are written first to their buffers. The circumstances that cause their internal registers to be updated with the values from the buffers are summarized as below table. Table 36-56.
PAGE 845
Chapter 36 Programmable Delay Block (PDB) CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 36-57. Registers Update with SC[LDMOD] = x1 36.4.6 Interrupts PDB can generate two interrupts, PDB interrupt and PDB sequence error interrupt. The following table summarizes the interrupts. Table 36-57. PDB Interrupt Summary Interrupt Flags Enable Bit PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and SC[DMAEN] = 0 PDB Sequence Error Interrupt CHnS[ERRm] SC[PDBEIE] = 1 36.4.
PAGE 846
Application Information values of total peripheral clocks that can be detected are even values; if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod(4) and so forth. If the applications need a really long delay value and use 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. K20 Sub-Family Reference Manual, Rev.
PAGE 847
Chapter 37 FlexTimer (FTM) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexTimer Module (FTM) is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. 37.1.
PAGE 848
Introduction FlexTimer input triggers can be from comparators, ADC or other sub modules to initiate timer functions automatically. These triggers can be linked in a variety of ways during integration of the sub modules so please note carefully the options available for used FlexTimer configuration.
PAGE 849
Chapter 37 FlexTimer (FTM) • Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of PWM signal) • The FTM channels can operate as pairs with equal outputs, pairs with complementary outputs, or independent channels (with independent outputs) • The deadtime insertion is available for each complementary pair • Generation of triggers (match trigger) • Software control of PWM outputs • Up to 4 fault inputs for global fault control • The polarity of each channel
PAGE 850
Introduction 37.1.4 Block Diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 850 Freescale Semiconductor, Inc.
PAGE 851
Chapter 37 FlexTimer (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock external clock phase A phase B PS prescaler 3(1, 2, 4, 8, 16, 32, 64 or 128) synchronizer Quadrature decoder QUADEN CPWMS CAPTEST INITTRIGEN CNTIN FAULTM[1:0] FFVAL[3:0] FAULTIE FAULTnEN* FFLTRnEN* FTM counter FAULTIN FAULTF FAULTFn* fault control fault input n* CH0IE CH0F input capture mode logic C0V input capture mode logic C1V DECAPEN COMBINE0 CPWMS MS1B:MS1A ELS1B:ELS1A
PAGE 852
FTM Signal Descriptions 37.2 FTM Signal Descriptions Table 37-1 shows the user-accessible signals for the FTM. Table 37-1. FTM Signal Descriptions Signal EXTCLK CHn FAULTj Description I/O External clock. FTM external clock can be selected to drive the FTM counter. I FTM channel (n), where n can be 7-0 I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input.
PAGE 853
Chapter 37 FlexTimer (FTM) defined for each pair of channels. Since there are several FAULTj inputs, maximum of 4 for the FTM module, each one of these inputs is activated by the FAULTjEN bit in the FLTCTRL register. 37.2.4 PHA — FTM Quadrature Decoder Phase A Input The quadrature decoder phase A input is used as the quadrature decoder mode is selected.
PAGE 854
Memory Map and Register Definition 37.3.2 Register Descriptions This section consists of register descriptions in address order. Accesses to reserved addresses result in transfer errors. Registers for absent channels are considered reserved. FTM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8000 Status and Control (FTM0_SC) 32 R/W 0000_0000h 37.3.3/ 860 4003_8004 Counter (FTM0_CNT) 32 R/W 0000_0000h 37.3.
PAGE 855
Chapter 37 FlexTimer (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8040 Channel (n) Value (FTM0_C6V) 32 R/W 0000_0000h 37.3.7/ 866 4003_8044 Channel (n) Status and Control (FTM0_C7SC) 32 R/W 0000_0000h 37.3.6/ 863 4003_8048 Channel (n) Value (FTM0_C7V) 32 R/W 0000_0000h 37.3.7/ 866 4003_804C Counter Initial Value (FTM0_CNTIN) 32 R/W 0000_0000h 37.3.
PAGE 856
Memory Map and Register Definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8090 FTM Inverting Control (FTM0_INVCTRL) 32 R/W 0000_0000h 37.3.25/ 900 4003_8094 FTM Software Output Control (FTM0_SWOCTRL) 32 R/W 0000_0000h 37.3.26/ 901 4003_8098 FTM PWM Load (FTM0_PWMLOAD) 32 R/W 0000_0000h 37.3.27/ 903 4003_9000 Status and Control (FTM1_SC) 32 R/W 0000_0000h 37.3.
PAGE 857
Chapter 37 FlexTimer (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9044 Channel (n) Status and Control (FTM1_C7SC) 32 R/W 0000_0000h 37.3.6/ 863 4003_9048 Channel (n) Value (FTM1_C7V) 32 R/W 0000_0000h 37.3.7/ 866 4003_904C Counter Initial Value (FTM1_CNTIN) 32 R/W 0000_0000h 37.3.8/ 867 4003_9050 Capture and Compare Status (FTM1_STATUS) 32 R/W 0000_0000h 37.3.
PAGE 858
Memory Map and Register Definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 32 R/W 0000_0000h 37.3.26/ 901 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 32 R/W 0000_0000h 37.3.27/ 903 400B_8000 Status and Control (FTM2_SC) 32 R/W 0000_0000h 37.3.3/ 860 400B_8004 Counter (FTM2_CNT) 32 R/W 0000_0000h 37.3.
PAGE 859
Chapter 37 FlexTimer (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400B_8048 Channel (n) Value (FTM2_C7V) 32 R/W 0000_0000h 37.3.7/ 866 400B_804C Counter Initial Value (FTM2_CNTIN) 32 R/W 0000_0000h 37.3.8/ 867 400B_8050 Capture and Compare Status (FTM2_STATUS) 32 R/W 0000_0000h 37.3.9/ 867 400B_8054 Features Mode Selection (FTM2_MODE) 32 R/W 0000_0004h 37.3.
PAGE 860
Memory Map and Register Definition FTM memory map (continued) Absolute address (hex) 400B_8098 Width Access (in bits) Register name FTM PWM Load (FTM2_PWMLOAD) 32 R/W Reset value Section/ page 0000_0000h 37.3.27/ 903 37.3.3 Status and Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module.
PAGE 861
Chapter 37 FlexTimer (FTM) FTMx_SC field descriptions (continued) Field Description 0 1 5 CPWMS Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-aligned PWM Select Selects CPWM mode. This mode configures the FTM to operate in up-down counting mode. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 4–3 CLKS FTM counter operates in up counting mode. FTM counter operates in up-down counting mode.
PAGE 862
Memory Map and Register Definition Addresses: FTM0_CNT is 4003_8000h base + 4h offset = 4003_8004h FTM1_CNT is 4003_9000h base + 4h offset = 4003_9004h FTM2_CNT is 400B_8000h base + 4h offset = 400B_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 COUNT W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_CNT field descriptions Field Description 31–16 Reserved Th
PAGE 863
Chapter 37 FlexTimer (FTM) FTMx_MOD field descriptions (continued) Field 15–0 MOD Description Modulo value 37.3.6 Channel (n) Status and Control (FTMx_CSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 37-67. Mode, Edge, and Level Selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration X X X XX 0 None Pin not used for FTM Table continues on the next page...
PAGE 864
Memory Map and Register Definition Table 37-67. Mode, Edge, and Level Selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 0 0 0 1 Input capture Capture on Rising Edge Only 1 1X 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge 1 Output compare 10 Clear Output on match 11 Set Output on match 10 Edge-aligned PWM X1 1 XX 10 0 XX 10 Center-aligned PWM 0 0 X0 X1 See the following table (Table 37-8).
PAGE 865
Chapter 37 FlexTimer (FTM) Table 37-68.
PAGE 866
Memory Map and Register Definition FTMx_CnSC field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. 4 MSA Channel Mode Select Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 37-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. 3 ELSB Edge or Level Select The functionality of ELSB and ELSA depends on the channel mode. See Table 37-7.
PAGE 867
Chapter 37 FlexTimer (FTM) FTMx_CnV field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 VAL Channel Value Captured FTM counter value of the input modes or the match value for the output modes 37.3.8 Counter Initial Value (FTMx_CNTIN) The Counter Initial Value register contains the initial value for the FTM counter. Writing to the CNTIN register latches the value into a buffer.
PAGE 868
Memory Map and Register Definition Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. CHF is cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
PAGE 869
Chapter 37 FlexTimer (FTM) FTMx_STATUS field descriptions (continued) Field Description 0 1 4 CH4F Channel 4 Flag See the register description. 0 1 3 CH3F See the register description. See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag See the register description. 0 1 0 CH0F No channel event has occurred. A channel event has occurred. Channel 2 Flag 0 1 1 CH1F No channel event has occurred. A channel event has occurred.
PAGE 870
Memory Map and Register Definition 37.3.10 Features Mode Selection (FTMx_MODE) This register contains the control bits used to configure the fault interrupt and fault control, capture test mode, PWM synchronization, write protection, channel output initialization, and enable the enhanced features of the FTM. These controls relate to all channels within this module.
PAGE 871
Chapter 37 FlexTimer (FTM) FTMx_MODE field descriptions (continued) Field 4 CAPTEST Description Capture Test Mode Enable Enables the capture test mode. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 3 PWMSYNC PWM Synchronization Mode Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization (PWM Synchronization). The PWMSYNC bit configures the synchronization when SYNCMODE is zero. 0 1 2 WPDIS No restrictions.
PAGE 872
Memory Map and Register Definition NOTE The software trigger (SWSYNC bit) and hardware triggers (TRIG0, TRIG1, and TRIG2 bits) have a potential conflict if used together when SYNCMODE = 0. It is recommended using only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen. The selection of the loading point (CNTMAX and CNTMIN bits) is intended to provide the update of MOD, CNTIN, and CnV registers across all enabled channels simultaneously.
PAGE 873
Chapter 37 FlexTimer (FTM) FTMx_SYNC field descriptions (continued) Field Description 0 1 6 TRIG2 PWM Synchronization Hardware Trigger 2 Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal. 0 1 5 TRIG1 Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 happens when a rising edge is detected at the trigger 1 input signal. Enables hardware trigger 0 to the PWM synchronization.
PAGE 874
Memory Map and Register Definition FTMx_SYNC field descriptions (continued) Field Description 0 1 The minimum loading point is disabled. The minimum loading point is enabled. 37.3.
PAGE 875
Chapter 37 FlexTimer (FTM) FTMx_OUTINIT field descriptions (continued) Field Description Selects the value that is forced into the channel output when the initialization occurs. 0 1 2 CH2OI The initialization value is 0. The initialization value is 1. Channel 2 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs. 0 1 1 CH1OI The initialization value is 0. The initialization value is 1.
PAGE 876
Memory Map and Register Definition FTMx_OUTMASK field descriptions Field 31–8 Reserved 7 CH7OM Description This read-only field is reserved and always has the value zero. Channel 7 Output Mask Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). 0 1 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally).
PAGE 877
Chapter 37 FlexTimer (FTM) FTMx_OUTMASK field descriptions (continued) Field Description 0 CH0OM Channel 0 Output Mask Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). 0 1 Channel output is not masked. It continues to operate normally. Channel output is masked. It is forced to its inactive state. 37.3.
PAGE 878
Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field 29 SYNCEN3 Description Synchronization Enable for n = 6 Enables PWM synchronization of registers C(n)V and C(n+1)V. 0 1 28 DTEN3 The PWM synchronization in this pair of channels is disabled. The PWM synchronization in this pair of channels is enabled. Deadtime Enable for n = 6 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 879
Chapter 37 FlexTimer (FTM) FTMx_COMBINE field descriptions (continued) Field 23 Reserved 22 FAULTEN2 Description This read-only field is reserved and always has the value zero. Fault Control Enable for n = 4 Enables the fault control in channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 21 SYNCEN2 Synchronization Enable for n = 4 Enables PWM synchronization of registers C(n)V and C(n+1)V.
PAGE 880
Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field Description 0 1 16 COMBINE2 The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Combine Channels for n = 4 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 15 Reserved 14 FAULTEN1 Channels (n) and (n+1) are independent.
PAGE 881
Chapter 37 FlexTimer (FTM) FTMx_COMBINE field descriptions (continued) Field Description 0 1 9 COMP1 The dual edge capture mode in this pair of channels is disabled. The dual edge capture mode in this pair of channels is enabled. Complement of Channel (n) for n = 2 Enables complementary mode for the combined channels. In complementary mode the channel (n+1) output is the inverse of the channel (n) output. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 882
Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field Description 2 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 Enables the dual edge capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in dual edge capture mode according to Table 37-7. This field applies only when FTMEN = 1. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 883
Chapter 37 FlexTimer (FTM) FTMx_DEADTIME field descriptions (continued) Field 7–6 DTPS Description Deadtime Prescaler Value Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0x 10 11 5–0 DTVAL Divide the system clock by 1. Divide the system clock by 4. Divide the system clock by 16. Deadtime Value Selects the deadtime insertion value for the deadtime counter.
PAGE 884
Memory Map and Register Definition Addresses: FTM0_EXTTRIG is 4003_8000h base + 6Ch offset = 4003_806Ch FTM1_EXTTRIG is 4003_9000h base + 6Ch offset = 4003_906Ch FTM2_EXTTRIG is 400B_8000h base + 6Ch offset = 400B_806Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved[bit 8] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRIGF INITTRIGEN CH1TRIG CH0TRIG CH5TRIG CH4TRIG CH3TRIG CH2TRIG W 0 0 0 0 0
PAGE 885
Chapter 37 FlexTimer (FTM) FTMx_EXTTRIG field descriptions (continued) Field Description Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. 0 1 2 CH4TRIG The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 4 Trigger Enable Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. 0 1 1 CH3TRIG The generation of the channel trigger is disabled.
PAGE 886
Memory Map and Register Definition FTMx_POL field descriptions Field 31–8 Reserved 7 POL7 Description This field is reserved. Channel 7 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 6 POL6 The channel polarity is active high. The channel polarity is active low. Channel 6 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 887
Chapter 37 FlexTimer (FTM) FTMx_POL field descriptions (continued) Field Description 0 1 0 POL0 The channel polarity is active high. The channel polarity is active low. Channel 0 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 The channel polarity is active high. The channel polarity is active low. 37.3.
PAGE 888
Memory Map and Register Definition FTMx_FMS field descriptions (continued) Field 7 FAULTF Description Fault Detection Flag Represents the logic OR of the individual FAULTFj bits (where j = 3, 2, 1, 0). Clear FAULTF by reading the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition at the enabled fault inputs. Writing a 1 to FAULTF has no effect.
PAGE 889
Chapter 37 FlexTimer (FTM) FTMx_FMS field descriptions (continued) Field Description 0 1 1 FAULTF1 No fault condition was detected at the fault input. A fault condition was detected at the fault input. Fault Detection Flag 1 Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault condition is detected at the fault input.
PAGE 890
Memory Map and Register Definition Addresses: FTM0_FILTER is 4003_8000h base + 78h offset = 4003_8078h FTM1_FILTER is 4003_9000h base + 78h offset = 4003_9078h FTM2_FILTER is 400B_8000h base + 78h offset = 400B_8078h Bit 31 30 29 28 27 26 25 R 23 22 21 20 19 18 17 16 15 Reserved W Reset 24 0 0 0 0 0 0 0 0 0 14 13 12 11 CH3FVAL 0 0 0 0 0 0 0 0 0 0 10 9 8 7 CH2FVAL 0 0 0 0 6 5 4 3 CH1FVAL 0 0 0 0 2 1 0 CH0FVAL 0 0 0 0 0 FTMx_FILTER field desc
PAGE 891
Chapter 37 FlexTimer (FTM) 37.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter.
PAGE 892
Memory Map and Register Definition FTMx_FLTCTRL field descriptions (continued) Field 5 FFLTR1EN Description Fault Input 1 Filter Enable Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 4 FFLTR0EN Fault input filter is disabled. Fault input filter is enabled. Fault Input 0 Filter Enable Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 893
Chapter 37 FlexTimer (FTM) 37.3.21 Quadrature Decoder Control and Status (FTMx_QDCTRL) This register has the control and status bits for the quadrature decoder mode.
PAGE 894
Memory Map and Register Definition FTMx_QDCTRL field descriptions (continued) Field Description 0 1 4 PHBPOL Phase B Input Polarity Selects the polarity for the quadrature decoder phase B input. 0 1 3 QUADMODE Selects the encoding mode used in the quadrature decoder mode. Indicates the counting direction. Counting direction is decreasing (FTM counter decrement). Counting direction is increasing (FTM counter increment).
PAGE 895
Chapter 37 FlexTimer (FTM) 37.3.22 Configuration (FTMx_CONF) This register selects the number of times that the FTM counter overflow should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use of an external global time base, and the global time base signal generation.
PAGE 896
Memory Map and Register Definition FTMx_CONF field descriptions (continued) Field Description 4–0 NUMTOF TOF Frequency Selects the ratio between the number of counter overflows to the number of times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for the next overflow. NUMTOF = 2: The TOF bit is set for the first counter overflow but not for the next 2 overflows.
PAGE 897
Chapter 37 FlexTimer (FTM) FTMx_FLTPOL field descriptions (continued) Field 2 FLT2POL Description Fault Input 2 Polarity Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 1 FLT1POL The fault input polarity is active high. A one at the fault input indicates a fault. The fault input polarity is active low. A zero at the fault input indicates a fault. Fault Input 1 Polarity Defines the polarity of the fault input.
PAGE 898
Memory Map and Register Definition 37.3.24 Synchronization Configuration (FTMx_SYNCONF) This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL and CNTIN registers synchronization, if FTM clears the TRIGj bit (where j = 0, 1, 2) when the hardware trigger j is detected.
PAGE 899
Chapter 37 FlexTimer (FTM) FTMx_SYNCONF field descriptions (continued) Field Description 16 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 15–13 Reserved This read-only field is reserved and always has the value zero. 12 SWSOC Software output control synchronization is activated by the software trigger. 11 SWINVC Inverting control synchronization is activated by the software trigger.
PAGE 900
Memory Map and Register Definition FTMx_SYNCONF field descriptions (continued) Field Description 0 1 1 Reserved CNTIN register is updated with its buffer value at all rising edges of system clock. CNTIN register is updated with its buffer value by the PWM synchronization. This read-only field is reserved and always has the value zero. 0 HWTRIGMODE Hardware Trigger Mode 0 1 FTM clears the TRIGj bit when the hardware trigger j is detected.
PAGE 901
Chapter 37 FlexTimer (FTM) FTMx_INVCTRL field descriptions (continued) Field Description 0 1 0 INV0EN Inverting is disabled. Inverting is enabled. Pair Channels 0 Inverting Enable 0 1 Inverting is disabled. Inverting is enabled. 37.3.26 FTM Software Output Control (FTMx_SWOCTRL) This register enables software control of channel (n) output and defines the value forced to the channel (n) output: • The CHnOC bits enable the control of the corresponding channel (n) output by software.
PAGE 902
Memory Map and Register Definition FTMx_SWOCTRL field descriptions (continued) Field Description 15 CH7OCV Channel 7 Software Output Control Value 14 CH6OCV Channel 6 Software Output Control Value 13 CH5OCV Channel 5 Software Output Control Value 12 CH4OCV Channel 4 Software Output Control Value 11 CH3OCV Channel 3 Software Output Control Value 10 CH2OCV Channel 2 Software Output Control Value 9 CH1OCV Channel 1 Software Output Control Value 8 CH0OCV Channel 0 Software Output Control Value
PAGE 903
Chapter 37 FlexTimer (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description 0 1 The channel output is not affected by software output control. The channel output is affected by software output control. 3 CH3OC Channel 3 Software Output Control Enable 2 CH2OC Channel 2 Software Output Control Enable 1 CH1OC Channel 1 Software Output Control Enable 0 CH0OC Channel 0 Software Output Control Enable 0 1 0 1 0 1 0 1 The channel output is not affected by software output control.
PAGE 904
Memory Map and Register Definition FTMx_PWMLOAD field descriptions Field 31–10 Reserved 9 LDOK Description This read-only field is reserved and always has the value zero. Load Enable Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers. 0 1 Loading updated values is disabled. Loading updated values is enabled. 8 Reserved This read-only field is reserved and always has the value zero.
PAGE 905
Chapter 37 FlexTimer (FTM) 37.4 Functional Description The following sections describe the FTM features. The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. FTM counting is up. Channel (n) is in high-true EPWM mode.
PAGE 906
Functional Description The fixed frequency clock is an alternative clock source for the FTM counter that allows the selection of a clock other than the system clock or an external clock. This clock input is defined by chip integration. Refer the chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency.
PAGE 907
Chapter 37 FlexTimer (FTM) 37.4.3.1 Up Counting Up counting is selected when (QUADEN = 0) and (CPWMS = 0). CNTIN defines the starting value of the count and MOD defines the final value of the count (see the following figure). The value of CNTIN is loaded into the FTM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with the value of CNTIN. The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the FTM counter clock.
PAGE 908
Functional Description FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter 3 4 0 1 2 3 4 0 1 2 3 0 4 1 2 TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 37-169.
PAGE 909
Chapter 37 FlexTimer (FTM) FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN FTM counter load of CNTIN 0x0005 0x0015 0x0016 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 ... TOF bit set TOF bit set TOF bit Figure 37-170. Example of Up Counting When the Value of CNTIN Is Greater Than the Value of MOD 37.4.3.2 Up-Down Counting Up-down counting is selected when (QUADEN= 0) and (CPWMS = 1).
PAGE 910
Functional Description FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 TOF bit set TOF bit period of FTM counter clock set TOF bit period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 37-171. Example of Up-Down Counting When CNTIN = 0x0000 Note It is expected that the up-down counting be used only with CNTIN = 0x0000. 37.4.3.
PAGE 911
Chapter 37 FlexTimer (FTM) 37.4.3.4 Counter Reset Any write to CNT resets the FTM counter to the value in the CNTIN register and the channels output to its initial value (except for channels in output compare mode). The FTM counter synchronization (see FTM Counter Synchronization) can also be used to force the value of CNTIN into the FTM counter and the channels output to its initial value (except for channels in output compare mode). 37.4.3.
PAGE 912
Functional Description When a selected edge occurs on the channel input, the current value of the FTM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1 (see the following figure). When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers inputcapture event.
PAGE 913
Chapter 37 FlexTimer (FTM) Firstly the input signal is synchronized by the system clock. Following synchronization, the input signal enters the filter block (see the following figure). When there is a state change in the input signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable on the input, the counter continues to increment. If the 5-bit counter overflows (the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of the input signal is validated.
PAGE 914
Functional Description 37.4.5 Output Compare Mode The output compare mode is selected when (DECAPEN = 0), (COMBINE = 0), (CPWMS = 0), and (MSnB:MSnA = 0:1). In output compare mode, the FTM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter matches the value in the CnV register of an output compare channel, the channel (n) output can be set, cleared, or toggled.
PAGE 915
Chapter 37 FlexTimer (FTM) MOD = 0x0005 CnV = 0x0003 channel (n) match counter overflow CNT ... channel (n) output 0 2 1 3 counter overflow 4 5 0 channel (n) match 1 2 3 counter overflow 4 5 0 1 ... previous value previous value CHnF bit TOF bit Figure 37-180. Example of the Output Compare Mode when the Match Sets the Channel Output It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0).
PAGE 916
Functional Description If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by FTM. If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter overflow (when the CNTIN register value is are loaded into the FTM counter), and it is forced low at the channel (n) match (FTM counter = CnV) (see the following figure).
PAGE 917
Chapter 37 FlexTimer (FTM) 37.4.7 Center-Aligned PWM (CPWM) Mode The center-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0), (COMBINE = 0), and (CPWMS = 1). The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the period is determined by 2 × (MOD − CNTIN)(see the following figure). MOD must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
PAGE 918
Functional Description counter overflow channel (n) match in down counting MOD = 0x0008 CnV = 0x0005 CNT ... 7 8 7 6 5 4 3 counter overflow channel (n) match in down counting channel (n) match in up counting 2 1 0 1 2 3 4 5 7 6 8 7 6 5 ... channel (n) output previous value CHnF bit TOF bit Figure 37-185.
PAGE 919
Chapter 37 FlexTimer (FTM) 37.4.8 Combine Mode The combine mode is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), and (CPWMS = 0). In combine mode, the channel (n) (an even channel) and channel (n+1) (the adjacent odd channel) are combined to generate a PWM signal in the channel (n) output. In the combine mode, the PWM period is determined by (MOD − CNTIN + 0x0001) and the PWM pulse width (duty cycle) is determined by (|C(n+1)V − C(n)V|).
PAGE 920
Functional Description FTM counter MOD C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-188. Channel (n) Output If (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-189.
PAGE 921
Chapter 37 FlexTimer (FTM) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 37-191. Channel (n) Output If (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) FTM counter MOD C(n+1)V C(n)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 37-192.
PAGE 922
Functional Description FTM counter C(n+1)V MOD CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-193. Channel (n) Output If C(n)V and C(n+1)V Are Not Between CNTIN and MOD FTM counter MOD C(n+1)V = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-194.
PAGE 923
Chapter 37 FlexTimer (FTM) FTM counter MOD C(n)V = C(n+1)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 37-195. Channel (n) Output If (C(n)V = C(n+1)V = CNTIN) MOD = C(n+1)V = C(n)V FTM counter CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 37-196.
PAGE 924
Functional Description FTM counter MOD C(n+1)V CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-198. Channel (n) Output If (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter MOD C(n)V CNTIN C(n+1)V channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-199. Channel (n) Output If (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD) K20 Sub-Family Reference Manual, Rev.
PAGE 925
Chapter 37 FlexTimer (FTM) FTM counter C(n)V MOD C(n+1)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-200. Channel (n) Output If (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)V MOD C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-201. Channel (n) Output If (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) K20 Sub-Family Reference Manual, Rev.
PAGE 926
Functional Description FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 not fully 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle Figure 37-202. Channel (n) Output If (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 37.4.8.
PAGE 927
Chapter 37 FlexTimer (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 37-203. Channel (n+1) Output in Complementary Mode with (ELSnB:ELSnA = 1:0) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = X:1 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 37-204.
PAGE 928
Functional Description If (CLKS[1:0] ≠ 0:0 and FTMEN = 0), then MOD register is updated according to the CPWMS bit, that is: • If the selected mode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN. If the FTM counter is at free-running counter mode then this update occurs when the FTM counter changes from 0xFFFF to 0x0000.
PAGE 929
Chapter 37 FlexTimer (FTM) • If the selected mode is output compare then CnV register is updated according to the SYNCEN bit. If (SYNCEN = 0) then CnV register is updated after CnV register was written at the next change of the FTM counter (end of the prescaler counting). If (SYNCEN = 1) then CnV register is updated by the CnV register synchronization (C(n)V and C(n+1)V Register Synchronization).
PAGE 930
Functional Description system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Note All hardware trigger inputs have the same behavior. Figure 37-205. Hardware Trigger Event with HWTRIGMODE = 0 If HWTRIGMODE = 1 then the TRIGn bit is only cleared when 0 is written to it. NOTE It is expected that the HWTRIGMODE bit be 1 only with enhanced PWM synchronization (SYNCMODE = 1). 37.4.11.
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Chapter 37 FlexTimer (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event PWM synchronization selected loading point Figure 37-206. Software Trigger Event 37.4.11.3 Boundary Cycle and Loading Points The boundary cycle definition is important for the loading points for the registers MOD, CNTIN and C(n)V. In up counting mode (Up Counting) the boundary cycle is defined as when the counter wraps to its initial value (CNTIN).
PAGE 932
Functional Description loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 37-207. Boundary Cycles and Loading Points 37.4.11.4 MOD Register Synchronization The MOD register synchronization updates the MOD register with its buffer value. This synchronization is enabled if (FTMEN = 1).
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Chapter 37 FlexTimer (FTM) begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization MOD register is updated by hardware trigger MOD register is updated by software trigger HWWRBUF = 0 bit ? SWWRBUF = 0 bit ? =1 =1 end software trigger 0= SWSYNC bit ? end hardware trigger TRIGn bit ? =1 =0 =1 FTM counter is reset by software trigger SWRSTCNT bit ? =1 wait hardware trigger n =0 wait the next selected loading point HWTRIGMODE bit ? =1 =0 update MOD with its
PAGE 934
Functional Description loading point. If the trigger event was a hardware trigger then the trigger enable bit (TRIGn) is cleared according to Hardware Trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 37-209.
PAGE 935
Chapter 37 FlexTimer (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 37-211. MOD Synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and (Software Trigger Was Used) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event MOD register is updated Figure 37-212.
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Functional Description 37.4.11.5 CNTIN Register Synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1) and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the MOD register synchronization done by the enhanced PWM synchronization (MOD Register Synchronization). 37.4.11.
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Chapter 37 FlexTimer (FTM) begin update OUTMASK register at each rising edge of system clock no = 0= SYNCHOM bit ? update OUTMASK register by PWM synchronization =1 1= rising edge of system clock ? SYNCMODE bit ? =0 legacy PWM synchronization = yes update OUTMASK with its buffer value end enhanced PWM synchronization OUTMASK is updated by hardware trigger OUTMASK is updated by software trigger 1= 0= SWSYNC bit ? SWOM bit ? software trigger =0 end 0= end HWOM bit ? =1 hardware trigger
PAGE 938
Functional Description If (SYNCMODE = 0), (SYNCHOM = 1) and (PWMSYNC = 0) then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware Trigger. Examples with software and hardware triggers follow.
PAGE 939
Chapter 37 FlexTimer (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 37-217. OUTMASK Synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and (a Hardware Trigger Was Used) 37.4.11.8 INVCTRL Register Synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value.
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Functional Description begin update INVCTRL register at each rising edge of system clock 0= INVC bit ? =1 update INVCTRL register by PWM synchronization 1= no = rising edge of system clock ? SYNCMODE bit ? =0 end = yes update INVCTRL with its buffer value end enhanced PWM synchronization INVCTRL is updated by hardware trigger INVCTRL is updated by software trigger 1= 0= SWSYNC bit ? SWINVC bit ? software trigger =0 end 0= end HWINVC bit ? hardware trigger end TRIGn bit ? =0 =1 =1
PAGE 941
Chapter 37 FlexTimer (FTM) The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits.
PAGE 942
Functional Description 37.4.11.10 FTM Counter Synchronization The FTM counter synchronization is a mechanism that allows the FTM to re-start the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value (except for channels in output compare mode) and the FTM counter is forced to its initial counting value defined by CNTIN register. The following figure shows the FTM counter synchronization.
PAGE 943
Chapter 37 FlexTimer (FTM) begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization FTM counter is reset by software trigger SWSYNC bit ? SWRSTCNT bit ? software trigger =0 end =0 1= FTM counter is reset by hardware trigger end HWRSTCNT bit ? =1 hardware trigger =0 update the channels outputs with their initial value clear SWSYNC bit =0 =1 =1 update FTM counter with CNTIN register value TRIGn bit ? wait hardware trigger n update FTM counter with CNTIN reg
PAGE 944
Functional Description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 37-222. FTM Counter Synchronization with (SYNCMODE = 0), (REINIT = 1), (PWMSYNC = 0), and (Software Trigger Was Used) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 37-223.
PAGE 945
Chapter 37 FlexTimer (FTM) 37.4.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1), where m represents a channel pair.
PAGE 946
Functional Description channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 37-226.
PAGE 947
Chapter 37 FlexTimer (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output after the software output control channel (n+1) output after the software output control CH(n)OC buffer CH(n+1)OC buffer write to SWOCTRL register write to SWOCTRL register CH(n)OC bit CH(n+1)OC bit SWOCTRL register synchronization SWOCTRL register synchronization NOTE CH(n)OCV = 1 and CH(n+1)OCV = 0. Figure 37-227.
PAGE 948
Functional Description Note • It is expected that the software output control feature be used only in combine mode. • The CH(n)OC and CH(n+1)OC bits should be equal. • The COMP bit should not be modified when software output control is enabled, that is, CH(n)OC = 1 and/or CH(n+1)OC = 1. • Software output control has the same behavior with disabled or enabled FTM counter (see the CLKS bitfield description in the Status and Control register). 37.4.
PAGE 949
Chapter 37 FlexTimer (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 37-228.
PAGE 950
Functional Description • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value). • and the deadtime delay is greater than or equal to the channel (n+1) duty cycle ((MOD – CNTIN + 1 – (C(n+1)V – C(n)V) ) × system clock), then the channel (n+1) output is always the inactive value (POL(n+1) bit value).
PAGE 951
Chapter 37 FlexTimer (FTM) 37.4.15 Output Mask The output mask can be used to force channels output to their inactive state through software (for example: to control a BLDC motor). Any write to the OUTMASK register updates its write buffer. The OUTMASK register is updated with its buffer value by PWM synchronization (OUTMASK Register Synchronization). If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value).
PAGE 952
Functional Description Note It is expected the output mask feature be used only in combine mode. 37.4.16 Fault Control The fault control is enabled if (FTMEN = 1) and (FAULTM[1:0] ≠ 0:0). FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select the value of the enabled filter in each enabled fault input.
PAGE 953
Chapter 37 FlexTimer (FTM) (FFVAL[3:0] 0000) and (FFLTRnEN*) FLTnPOL synchronizer fault input n* value 0 fault input n* system clock D CLK Q D Q CLK Fault filter (5-bit counter) 1 fault input polarity control rising edge detector FAULTFn* * where n = 3, 2, 1, 0 Figure 37-233. Fault Input n Control Block Diagram If the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, then the FAULTFn bit is set.
PAGE 954
Functional Description 37.4.16.1 Automatic Fault Clearing If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins (see the following figure).
PAGE 955
Chapter 37 FlexTimer (FTM) the beginning of new PWM cycles FTM counter channel (n) output (before fault control) FAULTIN bit channel (n) output (after fault control with manual fault clearing and POLn=0) FAULTF bit FAULTF bit is cleared NOTE The channel (n) output is after the fault control with manual fault clearing and POLn = 0. Figure 37-236. Fault Control with Manual Fault Clearing 37.4.16.3 Fault Inputs Polarity Control The FLTjPOL bit selects the fault input j polarity (where j = 0, 1, 2, 3).
PAGE 956
Functional Description Note It is expected that the polarity control be used only in combine mode. 37.4.18 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. The initialization depends on COMP and DTEN bits. The following table shows the values that channels (n) and (n+1) are forced by initialization when the COMP and DTEN bits are zero. Table 37-245.
PAGE 957
Chapter 37 FlexTimer (FTM) pair channels (m) - channels (n) and (n+1) FTM counter QUADEN DECAPEN COMBINE(m) CPWMS C(n)V MS(n)B CH(n)OC MS(n)A CH(n)OCV POL(n) ELS(n)B CH(n+1)OC POL(n+1) ELS(n)A CH(n)OI CH(n+1)OI COMP(m) INV(m)EN CH(n+1)OCV CH(n)OM DTEN(m) CH(n+1)OM FAULTEN(m) channel (n) output signal generation of channel (n) output signal initialization complementary mode inverting software output control deadtime insertion output mask fault control polarity control channel (n+1) o
PAGE 958
Functional Description The FTM is able to generate multiple triggers in one PWM period. Since each trigger is generated for a specific channel, several channels are required to implement this functionality. This behavior is described in the following figure.
PAGE 959
Chapter 37 FlexTimer (FTM) • When there is a write to CNT register • When there is the FTM counter synchronization (FTM Counter Synchronization) • If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The following figures show the cases. CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock FTM counter 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger Figure 37-239.
PAGE 960
Functional Description CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x00 FTM counter CLKS[1:0] bits 00 0x01 0x02 0x03 0x04 0x05 01 initialization trigger Figure 37-242. Initialization Trigger Is Generated If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a Value Different From Zero Is Written to CLKS[1:0] Bits The initialization trigger output provides a trigger signal that is used for on-chip modules. Note It is expected that the initialization trigger be used only in combine mode. 37.4.
PAGE 961
Chapter 37 FlexTimer (FTM) FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AC 0x78AD 0x78AE0x78AF 0x78B0 write 0x78AC write to CNT CHnF bit 0x78AC 0x0300 CnV NOTE - FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and (MOD = 0xFFFF) - FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 37-243. Capture Test Mode 37.4.
PAGE 962
Functional Description Table 37-248. Clear CHnF Bit when DMA = 1 CHnIE How CHnF Bit Can Be Cleared 0 CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and then writing a 0 to CHnF bit. 1 CHnF bit is cleared when the channel DMA transfer is done. 37.4.24 Dual Edge Capture Mode The dual edge capture mode is selected if FTMEN = 1 and DECAPEN = 1.
PAGE 963
Chapter 37 FlexTimer (FTM) The C(n)V register stores the value of FTM counter when the selected edge by channel (n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM counter when the selected edge by channel (n+1) is detected at channel (n) input. In this mode, the pair channels coherency mechanism ensures coherent data when the C(n)V and C(n+1)V registers are read. The only requirement is that C(n)V must be read before C(n+1)V.
PAGE 964
Functional Description 37.4.24.2 Continuous Capture Mode The continuous capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 1). In this capture mode, the edges at the channel (n) input are captured continuously. The ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A bits select the final edge to be captured. The edge captures are enabled while DECAP bit is set.
PAGE 965
Chapter 37 FlexTimer (FTM) 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 15 2 4 6 8 10 16 19 CH(n)F bit clear CH(n)F C(n+1)V 20 22 24 CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
PAGE 966
Functional Description 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 11 15 19 21 23 2 4 6 8 10 12 16 20 22 24 CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 37-246.
PAGE 967
Chapter 37 FlexTimer (FTM) The following figure shows an example of the dual edge capture – one-shot mode used to measure the period between two consecutive rising edges. The DECAPEN bit selects the dual edge capture mode, so it keeps set in all operation mode. The DECAP bit is set to enable the measurement of next period. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits.
PAGE 968
Functional Description edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set when the second rising edge is detected, that is, the edge selected by ELS(n +1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)V and C(n+1)V registers are ready for reading.
PAGE 969
Chapter 37 FlexTimer (FTM) When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)V register when a falling edge occurs in the channel (n) input signal. C(n)V register has the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred.
PAGE 970
Functional Description (CH(n)FVAL[3:0] bits in FILTER0 register). The phase B input filter is enabled by PHBFLTREN bit and this filter’s value is defined by CH1FVAL[3:0] bits (CH(n +1)FVAL[3:0] bits in FILTER0 register). Except for CH0FVAL[3:0] and CH1FVAL[3:0] bits, no channel logic is used in quadrature decoder mode.
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Chapter 37 FlexTimer (FTM) phase B (counting direction) phase A (counting rate) FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time Figure 37-251. Quadrature Decoder – Count and Direction Encoding Mode If QUADMODE = 0, then the phase A and phase B encoding mode (see the following figure) is enabled.
PAGE 972
Functional Description phase A phase B FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 FTM counter MOD CNTIN 0x0000 Time Figure 37-252. Quadrature Decoder – Phase A and Phase B Encoding Mode The following figure shows the FTM counter overflow in up counting. In this case, when the FTM counter changes from MOD to CNTIN, TOF and TOFDIR bits are set. TOF bit indicates the FTM counter overflow occurred.
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Chapter 37 FlexTimer (FTM) phase A phase B FTM counter increment/decrement -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time set TOF clear TOFDIR set TOF clear TOFDIR Figure 37-254. FTM Counter Overflow in Down Counting for Quadrature Decoder Mode 37.4.25.1 Quadrature Decoder Boundary Conditions The following figures are examples of motor jittering which causes the FTM counter transitions as indicated by these figures.
PAGE 974
Functional Description The following figure shows motor jittering produced by the phase B and A pulses respectively. The first highlighted transition causes a jitter on the FTM counter value near the maximum count value (MOD). The second indicated transition occurs on phase A and causes the FTM counter transition between the maximum and minimum count values which are defined by MOD and CNTIN registers. phase A phase B FTM counter MOD CNTIN 0x0000 Time Figure 37-256.
PAGE 975
Chapter 37 FlexTimer (FTM) Table 37-249.
PAGE 976
Functional Description After enabling the loading points, the LDOK bit needs to be set for the load to occur. In this case the load occurs at the next enabled loading point according to the following conditions: • If a new value was written to the MOD register, then the MOD register is updated with its write buffer value. • If a new value was written to the CNTIN register and CNTINC = 1, then the CNTIN register is updated with its write buffer value.
PAGE 977
Chapter 37 FlexTimer (FTM) • • • • NOTE If ELSjB and ELSjA bits are different from zero, then the channel (j) output signal is generated according to the configured output mode. If ELSjB and ELSjA bits are zero, then the generated signal is not available on channel (j) output. If CHjIE = 1, then the channel (j) interrupt is generated when the channel (j) match occurs. At the intermediate load neither the channels outputs nor the FTM counter are changed.
PAGE 978
Reset Overview In the configuration described in the preceding figure, FTM modules A and B have their FTM counters enabled if at least one of the gtb_out signals from one of the FTM modules is 1. There are several possible configurations for the interconnection of the gtb_in and gtb_out signals (represented by the example glue logic shown in the figure). Note that these configurations are chip-dependent and implemented outside of the FTM modules.
PAGE 979
Chapter 37 FlexTimer (FTM) When the FTM exits from reset: • the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] = 00b); • the timer overflow interrupt is zero (Timer Overflow Interrupt); • the channels interrupts are zero (Channel (n) Interrupt); • the fault interrupt is zero (Fault Interrupt); • the channels are in input capture mode (Input Capture Mode); • the channels outputs are zero; • the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) ().
PAGE 980
FTM Interrupts The following figure shows an example when the channel (n) is in output compare mode and the channel (n) output is toggled when there is a match. In the output compare mode, the channel output is not updated to its initial value when there is a write to CNT register (item 3). In this case, it is recommended to use the software output control (Software Output Control) or the initialization (Initialization) to update the channel output to the selected value (item 4).
PAGE 981
Chapter 37 FlexTimer (FTM) 37.6.3 Fault Interrupt The fault interrupt is generated when (FAULTIE = 1) and (FAULTF = 1). K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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FTM Interrupts K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 982 Freescale Semiconductor, Inc.
PAGE 983
Chapter 38 Periodic Interrupt Timer (PIT) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PIT timer module is an array of timers that can be used to raise interrupts and trigger DMA channels. 38.1.1 Block Diagram The following figure shows the PIT block diagram. K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Signal Description PIT Peripheral Bus PIT Registers load_value Timer 1 Iinterrupts Triggers Timer n Peripheral Bus Clock Figure 38-1. Block diagram of the PIT NOTE Refer to the Chip Configuration information for the number of PIT channels used in this MCU. 38.1.2 Features The main features of this block are: • Timers can generate DMA trigger pulses • Timers can generate interrupts • All interrupts are maskable • Independent timeout periods for each timer 38.
PAGE 985
Chapter 38 Periodic Interrupt Timer (PIT) 38.3 Memory Map/Register Description This section provides a detailed description of all registers accessible in the PIT module. NOTE Reserved registers will read as 0, writes will have no effect. NOTE Refer to the Chip Configuration information for the number of PIT channels used in this MCU.
PAGE 986
Memory Map/Register Description PIT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_7130 Timer Load Value Register (PIT_LDVAL3) 32 R/W 0000_0000h 38.3.2/ 987 4003_7134 Current Timer Value Register (PIT_CVAL3) 32 R/W 0000_0000h 38.3.3/ 987 4003_7138 Timer Control Register (PIT_TCTRL3) 32 R/W 0000_0000h 38.3.4/ 988 4003_713C Timer Flag Register (PIT_TFLG3) 32 R/W 0000_0000h 38.3.5/ 988 38.3.
PAGE 987
Chapter 38 Periodic Interrupt Timer (PIT) 38.3.2 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts.
PAGE 988
Memory Map/Register Description 38.3.4 Timer Control Register (PIT_TCTRLn) These register contain the control bits for each timer.
PAGE 989
Chapter 38 Periodic Interrupt Timer (PIT) PIT_TFLGn field descriptions Field 31–1 Reserved 0 TIF Description This read-only field is reserved and always has the value zero. Timer Interrupt Flag. TIF is set to 1 at the end of the timer period. This flag can be cleared only by writing it with 1. Writing 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request. 0 1 Time-out has not yet occurred. Time-out has occurred. 38.
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Functional Description Timer Enabled Start Value = p1 Disable Timer Re-Enable Timer Trigger Event p1 p1 p1 p1 Figure 38-23. Stopping and Starting a Timer The counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see the following figure). Disable Re-Enable Timer, Timer Set new Load Value Timer Enabled Start Value = p1 Trigger Event p2 p1 p2 p2 p1 Figure 38-24.
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Chapter 38 Periodic Interrupt Timer (PIT) 38.4.2 Interrupts All of the timers support interrupt generation. Refer to the MCU specification for related vector addresses and priorities. Timer interrupts can be enabled by setting the TIE bits. The timer interrupt flags (TIF) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that TIF bit. 38.5 Initialization and Application Information In the example configuration: • The PIT clock has a frequency of 50 MHz.
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Initialization and Application Information PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles PIT_TCTRL3 |= TEN; // start Timer 3 K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 992 Freescale Semiconductor, Inc.
PAGE 993
Chapter 39 Low power timer (LPTMR) 39.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The low power timer (LPTMR) can be configured to operate as a time counter (with optional prescaler) or as a pulse counter (with optional glitch filter) across all power modes, including the low leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. 39.1.
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LPTMR signal descriptions 39.1.2.2 Wait mode In wait mode, the LPTMR continues to operate normally and may be configured to exit the low power mode by generating an interrupt request. 39.1.2.3 Stop mode In stop mode, the LPTMR continues to operate normally and may be configured to exit the low power mode by generating an interrupt request. 39.1.2.
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Chapter 39 Low power timer (LPTMR) 39.2.1 Detailed signal descriptions Table 39-2. LPTMR interface-detailed signal descriptions Signal I/O LPTMR_ALTn I Description Pulse counter input. The LPTMR can select one of the input pins to be used in pulse counter mode. State meaning Assertion-If configured for pulse counter mode with active high input then assertion causes the LPTMR counter register to increment.
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Memory map and register definition 39.3.
PAGE 997
Chapter 39 Low power timer (LPTMR) LPTMRx_CSR field descriptions (continued) Field Description The Timer Pin Polarity configures the polarity of the input source in Pulse Counter mode. The Timer Pin Polarity should only be changed when the LPTMR is disabled. 0 1 2 TFC Pulse Counter input source is active high, and LPTMR Counter Register will increment on the rising edge. Pulse Counter input source is active low, and LPTMR Counter Register will increment on the falling edge.
PAGE 998
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field 6–3 PRESCALE Description Prescale Value The Prescaler Value register field configures the size of the Prescaler (in Time Counter mode) or width of the Glitch Filter (in Pulse Counter mode). The Prescale Value should only be altered when the LPTMR is disabled.
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Chapter 39 Low power timer (LPTMR) LPTMRx_PSR field descriptions (continued) Field Description 00 01 10 11 Prescaler/glitch filter clock 0 selected Prescaler/glitch filter clock 1 selected Prescaler/glitch filter clock 2 selected Prescaler/glitch filter clock 3 selected 39.3.
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Functional description LPTMRx_CNR field descriptions (continued) Field 15–0 COUNTER Description Counter Value The LPTMR Counter Register returns the current value of the LPTMR Counter. 39.4 Functional description 39.4.1 LPTMR power and reset The LPTMR remains powered in all power modes, including low leakage modes. If the LPTMR is not required to remain operating during a low power mode, then it should be disabled before entering the mode. The LPTMR is reset only on global POR or LVD.
PAGE 1001
Chapter 39 Low power timer (LPTMR) 39.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in time counter mode and as a glitch filter in pulse counter mode. The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled. 39.4.3.1 Prescaler enabled In time counter mode when the prescaler is enabled, the output of the prescaler directly clocks the LPTMR counter register.
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Functional description 39.4.3.4 Glitch filter bypassed In pulse counter mode when the glitch filter is bypassed, the selected input source increments the LPTMR counter register every time it asserts. Before the LPTMR is first enabled, the selected input source is forced to asserted. This is to prevent the LPTMR counter register from incrementing if the selected input source is already asserted when the LPTMR is first enabled. 39.4.
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Chapter 39 Low power timer (LPTMR) The LPTMR counter register cannot be initialized, but can be read at any time. Reading the LPTMR counter register at the same time as it is incrementing may return invalid data due to synchronization of the read data bus. If it is necessary for software to read the LPTMR counter register, it is recommended that two read accesses are performed and software verifies that the same data was returned for both reads. 39.4.
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Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1004 Freescale Semiconductor, Inc.
PAGE 1005
Chapter 40 Carrier Modulator Transmitter (CMT) 40.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The carrier modulator transmitter (CMT) module provides means to generate the protocol timing and carrier signals for a wide variety of encoding schemes.
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Block Diagram • Extended space operation in time, baseband, and FSK modes • Selectable input clock divider • Interrupt on end of cycle • Ability to disable CMT_IRO signal and use as timer interrupt 40.3 Block Diagram The following figure is the CMT block diagram. CMT Car r ier Gener ator Modulator CMT_IRO CMT Interrupts CMT Registers divider_enable Peripheral bus clock Clock Divider Peripheral bus Figure 40-1. CMT Module Block Diagram K20 Sub-Family Reference Manual, Rev.
PAGE 1007
Chapter 40 Carrier Modulator Transmitter (CMT) 40.4 Modes of Operation The CMT module operates in the following modes. • Time—When operating in time mode, the user independently defines the high and low times of the carrier signal to determine both period and duty cycle. • Baseband—When MSC[BASE] bit is set, the carrier output (fcg) to the modulator is held high continuously to allow for the generation of baseband protocols.
PAGE 1008
Modes of Operation NOTE The assignment of module modes to core modes is chipspecific. For module-to-core mode assignments, see the chapter that describes how modules are configured. 40.4.1 Wait Mode Operation During wait mode, the CMT if enabled, will continue to operate normally . However, there is no change in operating modes of CMT while in wait mode, because the CPU is not operating. 40.4.2 Stop Mode Operation This section describes the CMT stop mode operations. 40.4.2.
PAGE 1009
Chapter 40 Carrier Modulator Transmitter (CMT) 40.5 CMT External Signal Descriptions This table shows the description of the external signal. Table 40-2. CMT Signal Descriptions Signal CMT_IRO Description I/O Infrared Output O 40.5.1 CMT_IRO — Infrared Output This output signal is driven by the modulator output when MSC[MCGEN] is set and OC[IROPEN] is set.
PAGE 1010
Memory Map/Register Definition CMT memory map Absolute address (hex) Register name 4006_2000 CMT Carrier Generator High Data Register 1 (CMT_CGH1) 8 4006_2001 CMT Carrier Generator Low Data Register 1 (CMT_CGL1) 4006_2002 Width Access (in bits) Reset value Section/ page R/W Undefined 40.6.1/ 1010 8 R/W Undefined 40.6.2/ 1011 CMT Carrier Generator High Data Register 2 (CMT_CGH2) 8 R/W Undefined 40.6.
PAGE 1011
Chapter 40 Carrier Modulator Transmitter (CMT) CMT_CGH1 field descriptions Field 7–0 PH Description Primary Carrier High Time Data Value When selected, these bits contain the number of input clocks required to generate the carrier high time period. When operating in Time mode, this register is always selected. When operating in FSK mode, this register and the secondary register pair are alternately selected under control of the modulator. The primary carrier high time value is undefined out of reset.
PAGE 1012
Memory Map/Register Definition 40.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2) This data register contain the secondary high value for generating the carrier output. Address: CMT_CGH2 is 4006_2000h base + 2h offset = 4006_2002h Bit 7 6 5 4 Read 2 1 0 x* x* x* x* SH Write Reset 3 x* x* x* x* * Notes: • x = Undefined at reset.
PAGE 1013
Chapter 40 Carrier Modulator Transmitter (CMT) 40.6.5 CMT Output Control Register (CMT_OC) This register is used to control the IRO signal of the CMT module. Address: CMT_OC is 4006_2000h base + 4h offset = 4006_2004h Bit Read Write Reset 7 6 5 IROL CMTPOL IROPEN 0 0 0 4 3 2 1 0 0 0 0 0 0 0 CMT_OC field descriptions Field 7 IROL 6 CMTPOL Description IRO Latch Control Reading IROL reads the state of the IRO latch.
PAGE 1014
Memory Map/Register Definition 40.6.6 CMT Modulator Status and Control Register (CMT_MSC) The MSC register contains the modulator and carrier generator enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status bit.
PAGE 1015
Chapter 40 Carrier Modulator Transmitter (CMT) CMT_MSC field descriptions (continued) Field 3 BASE Description Baseband Enable When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. When BASE is cleared, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. This bit is cleared by reset.
PAGE 1016
Memory Map/Register Definition CMT_CMD1 field descriptions Field 7–0 MB[15:8] Description These bits control the upper mark periods of the modulator for all modes. 40.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2) The contents of this register are transferred to the modulator down counter upon the completion of a modulation period.
PAGE 1017
Chapter 40 Carrier Modulator Transmitter (CMT) CMT_CMD3 field descriptions Field 7–0 SB[15:8] Description These bits control the upper space periods of the modulator for all modes. 40.6.10 CMT Modulator Data Register Space Low (CMT_CMD4) The contents of this register are transferred to the space period register upon the completion of a modulation period.
PAGE 1018
Memory Map/Register Definition CMT_PPS field descriptions (continued) Field Description The primary prescaler divides the CMT clock to generate the Intermediate Frequency clock enable to the secondary prescaler.
PAGE 1019
Chapter 40 Carrier Modulator Transmitter (CMT) CMT_DMA field descriptions (continued) Field Description 0 1 DMA transfer request and done are disabled DMA transfer request and done are enabled 40.7 Functional Description The CMT module consists primarily of clock divider, carrier generator and modulator. 40.7.1 Clock Divider The CMT was originally designed to be based on 8 MHz bus clock that could be divided by 1, 2, 4 or 8 times accordingly with the specification.
PAGE 1020
Functional Description Table 40-17. Clock Divider Min. Min. Carrier Generator Period Modulator Period (μs) (μs) 0.125 0.25 1.0 01 0.25 0.5 2.0 8 10 0.5 1.0 4.0 8 11 1.0 2.0 8.0 Bus Clock (MHz) MSC[CMTDIV] 8 00 8 Carrier Generator Resolution (μs) The possible duty cycle options depend upon the number of counts required to complete the carrier period. For example, 1.6 MHz signal has a period of 625 ns and will therefore require 5 x 125 ns counts to generate.
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Chapter 40 Carrier Modulator Transmitter (CMT) SECONDARY HIGH COUNT REGISTER PRIMARY HIGH COUNT REGISTER CLO CK AND O UTPUT CO NTRO L =? CMTCLK BASE FSK MCGEN CLK CLR CARRIER OUT (fcg) 8-BIT UP COUNTER PRIMARY/ SECONDARY SELECT =? SECONDARY LOW COUNT REGISTER PRIMARY LOW COUNT REGISTER Figure 40-15. Carrier Generator Block Diagram The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register.
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Functional Description The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period. 40.7.3 Modulator The modulator block controls the state of the infrared out signal (IRO) . The modulator output is gated on to the IRO signal when the modulator/carrier generator is enabled .
PAGE 1023
Chapter 40 Carrier Modulator Transmitter (CMT) The activation of modulation space period is done when the carrier signal is low to prohibit cutting off the high pulse of a carrier signal. If the carrier signal is high, the modulator extends the mark period until the carrier signal become low. To de-assert the space period and assert the mark period, the carrier signal must have gone low to assure that a space period is not erroneously shortened.
PAGE 1024
Functional Description tmark = (CMD1:CMD2 + 1) ÷ (fCMTCLK ÷ 8) tspace = CMD3:CMD4 ÷ (fCMTCLK ÷ 8) where CMD1:CMD2 and CMD3:CMD4 are the decimal values of the concatenated registers. CMTCLK 8 C A R R IE R O U T (fcg) M O DULATO R G ATE MARK SPACE MARK IRO SIGNAL (TIME MODE) IRO SIGNAL (BASEBAND MODE) Figure 40-17. Example: CMT Output in Time and Baseband Modes with OC[CMTPOL]=0 40.7.3.
PAGE 1025
Chapter 40 Carrier Modulator Transmitter (CMT) Note The waveforms in Figure 40-17 and Figure 40-18 are for the purpose of conceptual illustration and are not meant to represent precise timing relationships between the signals shown. 40.7.3.3 FSK Mode When the modulator operates in FSK mode (MSC[MCGEN] and MSC[FSK] bits are set, and MSC[BASE] bit is cleared), the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero).
PAGE 1026
Functional Description CARRIER OUT (fcg) MARK1 MODULATOR GATE SPACE1 MARK2 SPACE2 MARK1 MARK2 SPACE1 IR O SIGNAL Figure 40-18. Example: CMT Output in FSK Mode 40.7.4 Extended Space Operation In either time, baseband or FSK mode, the space period can be made longer than the maximum possible value of the space period register .
PAGE 1027
Chapter 40 Carrier Modulator Transmitter (CMT) SET EXSPC CLEAR EXSPC Figure 40-19. Extended Space Operation 40.7.4.2 EXSPC Operation in FSK Mode In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and secondary registers at the end of each modulation period.
PAGE 1028
CMT Interrupts and DMA MSC[EOCF] is set when: • The modulator is not currently active and MSC[MCGEN] bit is set to begin the initial CMT transmission • At the end of each modulation cycle (when the counter is reloaded from CMD1:CMD2) while MSC[MCGEN] bit is set In the case where MSC[MCGEN] bit is cleared and then set before the end of the modulation cycle, MSC[EOCF] bit will not be set when MSC[MCGEN] is set, but will become set at the end of the current modulation cycle.
PAGE 1029
Chapter 41 Real Time Clock (RTC) 41.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 41.1.1 Features The RTC module features include: • Independent power supply, POR and 32 kHz crystal oscillator • 32-bit seconds counter with roll-over protection and 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.
PAGE 1030
Register definition During chip power-down, RTC is powered from the backup power supply (VBAT) and is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the RTC registers. The RTC registers are not accessible. During chip power-up, RTC remains powered from the backup power supply (VBAT). All RTC registers are accessible by software and all functions are operational. If enabled, the 32.
PAGE 1031
Chapter 41 Real Time Clock (RTC) Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. Read accesses by non-supervisor mode software complete as normal. Writing to a register protected by the write access register or lock register does not generate a bus error, but the write will not complete.
PAGE 1032
Register definition RTC_TSR field descriptions Field Description 31–0 TSR Time Seconds Register When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is disabled will clear the SR[TOF] and/or the SR[TIF].
PAGE 1033
Chapter 41 Real Time Clock (RTC) RTC_TAR field descriptions (continued) Field Description When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the SR[TAF]. 41.2.
PAGE 1034
Register definition 41.2.
PAGE 1035
Chapter 41 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description 9 CLKO Clock Output 8 OSCE Oscillator Enable 7–4 Reserved 3 UM 0 1 0 1 The 32kHz clock is output to other peripherals The 32kHz clock is not output to other peripherals 32.768 kHz oscillator is disabled. 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
PAGE 1036
Register definition 41.2.
PAGE 1037
Chapter 41 Real Time Clock (RTC) 41.2.
PAGE 1038
Register definition 41.2.
PAGE 1039
Chapter 41 Real Time Clock (RTC) 41.2.
PAGE 1040
Register definition RTC_WAR field descriptions (continued) Field Description 1 TPRW Time Prescaler Register Write Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset. 0 1 0 TSRW Writes to the time prescaler register are ignored. Writes to the time prescaler register complete as normal. Time Seconds Register Write Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
PAGE 1041
Chapter 41 Real Time Clock (RTC) RTC_RAR field descriptions (continued) Field 4 CRR Description Control Register Read Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset. 0 1 3 TCRR Time Compensation Register Read Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset 0 1 2 TARR Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
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Functional description The RTC includes its own analog POR block, which generates a power-on-reset signal whenever the RTC module is powered up and initializes all RTC registers to their default state. A software reset bit can also initialize all RTC registers. The RTC also monitors the chip power supply and electrically isolates itself when the rest of the chip is powered down.
PAGE 1043
Chapter 41 Real Time Clock (RTC) The time seconds register and time prescaler register can only be written when the SR[TCE] bit is clear. Always write to the prescaler register before writing to the seconds register, since the seconds register increments on the falling edge of bit 14 of the prescaler register. The time prescaler register increments provided the SR[TCE] bit is set, the SR[TIF] is clear, the SR[TOF] is clear and the 32.768 kHz clock source is present.
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Functional description Updates to the time compensation register will not take effect until the next time the time seconds register increments and provided the previous compensation interval has expired. When the compensation interval is set to other than once a second then the compensation is applied in the first second interval and the remaining second intervals receive no compensation. Compensation is disabled by configuring the time compensation register to zero. 41.3.
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Chapter 41 Real Time Clock (RTC) 41.3.7 Access control The read access and write access registers are implemented in the chip power domain and reset on the chip reset (they are not affected by the VBAT POR or the software reset). They are used to block read or write accesses to each register until the next chip system reset. When accesses are blocked the bus access is not seen in the VBAT power supply and does not generate a bus error. 41.3.
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Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1046 Freescale Semiconductor, Inc.
PAGE 1047
Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section describes the USB. The OTG implementation in this module provides limited host functionality as well as device solutions for implementing a USB 2.0 fullspeed/low-speed compliant peripheral. The OTG implementation supports the On-TheGo (OTG) addendum to the USB 2.0 Specification.
PAGE 1048
Introduction The host initiates transactions to specific peripherals, while the device responds to control transactions. The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mb/s or 1.5 Mb/s. For additional information, refer to the USB 2.0 specification. Host PC External Hub External Hub Root Hub Host Software USB Cable USB Cable USB Cables USB Cable USB Peripherals Figure 42-1. Example USB 2.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Print Photos Keyboard Input Swap Songs Hot Sync Figure 42-2. Example USB 2.0 On-The-Go Configurations 42.1.3 USB-FS Features • USB 1.1 and 2.0 compliant full-speed device controller • 16-Bidirectional end points • DMA or FIFO data stream interfaces • Low-power consumption • On-The-Go protocol logic 42.2 Functional Description The USB-FS 2.
PAGE 1050
Programmers Interface 42.2.1 Data Structures The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications the USB-FS implements a Buffer Descriptor Table (BDT) in system memory. See Figure 42-3. 42.3 Programmers Interface This section discusses the major components of the programming model for the USB module. 42.3.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) System Memory BDT_PAGE Registers END_POINT IN ODD 000 BDT Page Current Endpoint BDT ••• Start of Buffer ••• Buffer in Memory Figure 42-3. Buffer Descriptor Table 42.3.2 Rx vs.
PAGE 1052
Programmers Interface Table 42-1. Data Direction for USB Host or USB Target (continued) Host Rx Tx IN Out or Setup 42.3.3 Addressing Buffer Descriptor Table Entries An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via the USB-FS or microprocessor. Some points of interest are: • • • • • • • The Buffer Descriptor Table occupies up to 512 bytes of system memory. 16 bidirectional endpoints can be supported with a full BDT of 512 bytes.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) The USB-FS Controller uses the data stored in the BDs to determine: • Who owns the buffer in system memory • Data0 or Data1 PID • Release Own upon packet completion • No address increment (FIFO Mode) • Data toggle synchronization enable • How much data is to be transmitted or received • Where the buffer resides in system memory While the microprocessor uses the data stored in the BDs to determine: • Who owns the buffer in system memory • Data0 or Data
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Programmers Interface Table 42-4. Buffer Descriptor Byte Fields (continued) Field 7 OWN Description The OWN bit determines whether the microprocessor or the USB-FS currently owns the buffer. Except when KEEP=1, the SIE writes a 0 to this bit when it has completed a token. This byte of the BD should always be the last byte the microprocessor updates when it initializes a BD. 0 The microprocessor has exclusive access to the BD. The USB-FS ignores all other fields in the BD.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Table 42-4. Buffer Descriptor Byte Fields (continued) Field 2 BDT_STALL TOK_PID[0] Description Setting this bit causes the USB-FS to issue a STALL handshake if a token is received by the SIE that would use the BDT in this location. The BDT is not consumed by the SIE (the owns bit remains set and the rest of the BDT is unchanged) when a BDT-STALL bit is set. • If KEEP=0, bit 0 of the current token PID is written back to the BD.
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Programmers Interface 5. When the microprocessor processes the TOK_DNE interrupt, it reads from the status register all the information needed to process the endpoint. 6. At this point, the microprocessor allocates a new BD so additional USB data can be transmitted or received for that endpoint, and then processes the last BD. The following figure shows a timeline of how a typical USB token is processed after the BDT is read and OWN=1.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Table 42-5. USB Responses to DMA Overrun Errors (continued) Errors due to Memory Latency Errors due to Oversized Packets — The data written to memory is clipped to the MaxPacket size so as not to corrupt system memory. The DMA_ERR bit is set in the ERR_STAT register for host and device modes of operation. Depending on the values of the INT_ENB and ERR_ENB register, the core may assert an interrupt to notify the processor of the DMA error.
PAGE 1058
Memory Map/Register Definitions USB memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_201C OTG Control Register (USB0_OTGCTL) 8 R/W 00h 42.4.8/ 1064 4007_2080 Interrupt Status Register (USB0_ISTAT) 8 R/W 00h 42.4.9/ 1065 4007_2084 Interrupt Enable Register (USB0_INTEN) 8 R/W 00h 42.4.10/ 1066 4007_2088 Error Interrupt Status Register (USB0_ERRSTAT) 8 R/W 00h 42.4.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USB memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_20D4 Endpoint Control Register (USB0_ENDPT5) 8 R/W 00h 42.4.23/ 1076 4007_20D8 Endpoint Control Register (USB0_ENDPT6) 8 R/W 00h 42.4.23/ 1076 4007_20DC Endpoint Control Register (USB0_ENDPT7) 8 R/W 00h 42.4.23/ 1076 4007_20E0 Endpoint Control Register (USB0_ENDPT8) 8 R/W 00h 42.4.
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Memory Map/Register Definitions USBx_PERID field descriptions Field 7–6 Reserved 5–0 ID Description This read-only field is reserved and always has the value zero. Peripheral identification bits These bits always read 0x04 (00_0100) 42.4.2 Peripheral ID Complement Register (USBx_IDCOMP) The Peripheral ID Complement Register reads back the complement of the Peripheral ID Register. For the USB Peripheral, this is the value 0xFB.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.4.4 Peripheral Additional Info Register (USBx_ADDINFO) The Peripheral Additional info Register reads back the value of the fixed Interrupt Request Level (IRQNUM) along with the Host Enable bit. If set to 1, the Host Enable bit indicates the USB peripheral is operating in host mode.
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Memory Map/Register Definitions USBx_OTGISTAT field descriptions (continued) Field 5 LINE_STATE_ CHG 4 Reserved Description This bit is set when the USB line state changes. The interrupt associated with this bit can be used to detect Reset, Resume, Connect, and Data Line Pulse signals. This read-only field is reserved and always has the value zero. 3 SESSVLDCHG This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGICR field descriptions (continued) Field 3 SESSVLDEN Description Session valid interrupt enable 0 1 The SESSVLDCHG interrupt is disabled. The SESSVLDCHG interrupt is enabled. 2 BSESSEN B Session END interrupt enable 1 Reserved This read-only field is reserved and always has the value zero.
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Memory Map/Register Definitions USBx_OTGSTAT field descriptions (continued) Field Description 0 1 4 Reserved The LINE_STAT_CHG bit is not yet stable. The LINE_STAT_CHG bit has been debounced and is stable. This read-only field is reserved and always has the value zero. 3 SESS_VLD Session valid 2 BSESSEND B Session END 0 1 0 1 1 Reserved The VBUS voltage is below the B session Valid threshold The VBUS voltage is above the B session Valid threshold.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGCTL field descriptions (continued) Field Description 0 1 D+ pulldown resistor is not enabled. D+ pulldown resistor is enabled. 4 DMLOW D- Data Line pull-down resistor enable 3 Reserved This read-only field is reserved and always has the value zero. 2 OTGEN 0 1 On-The-Go pullup/pulldown resistor enable 0 1 1–0 Reserved D- pulldown resistor is not enabled. D- pulldown resistor is enabled.
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Memory Map/Register Definitions USBx_ISTAT field descriptions (continued) Field Description This bit is set when the USB Module detects an attach of a USB device. This signal is only valid if HOSTMODEEN is true. This interrupt signifies that a peripheral is now present and must be configured. 5 RESUME This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the USB bus. When not in suspend mode this interrupt should be disabled.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_INTEN field descriptions (continued) Field 5 RESUMEEN 4 SLEEPEN Description RESUME Interrupt Enable 0 1 The RESUME interrupt is not enabled. The RESUME interrupt is enabled. SLEEP Interrupt Enable 0 1 The SLEEP interrupt is not enabled. The SLEEP interrupt is enabled.
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Memory Map/Register Definitions USBx_ERRSTAT field descriptions Field Description 7 BTSERR This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the error. 6 Reserved This read-only field is reserved and always has the value zero. 5 DMAERR This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_ERREN field descriptions Field 7 BTSERREN 6 Reserved Description BTSERR Interrupt Enable 0 1 The BTSERR interrupt is not enabled. The BTSERR interrupt is enabled. This read-only field is reserved and always has the value zero. 5 DMAERREN DMAERR Interrupt Enable 4 BTOERREN BTOERR Interrupt Enable 3 DFN8EN 2 CRC16EN 1 CRC5EOFEN 0 PIDERREN 0 1 0 1 The DMAERR interrupt is not enabled. The DMAERR interrupt is enabled.
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Memory Map/Register Definitions 42.4.13 Status Register (USBx_STAT) The Status Register reports the transaction status within the USB Module. When the processor's interrupt controller has received a TOKDNE interrupt the Status Register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOKDNE interrupt bit is asserted. The STAT register is actually a read window into a status FIFO maintained by the USB Module.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.4.14 Control Register (USBx_CTL) The Control Register provides various control and configuration information for the USB Module.
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Memory Map/Register Definitions USBx_CTL field descriptions (continued) Field Description 0 USBENSOFEN USB Enable Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much of the logic in the SIE. When host mode is enabled, clearing this bit causes the SIE to stop sending SOF tokens. 0 The USB Module is disabled. 1 The USB Module is enabled. 42.4.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.4.16 BDT Page Register 1 (USBx_BDTPAGE1) The Buffer Descriptor Table Page Register 1 provides address bits 15 through 9 of the base address where the current Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always taken as zero.
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Memory Map/Register Definitions 42.4.18 Frame Number Register High (USBx_FRMNUMH) The Frame Number Register (Low and High) contains an 11-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_TOKEN field descriptions Field 7–4 TOKENPID 3–0 TOKENENDPT Description This 4-bit field contains the token type executed by the USB Module. 0001 1001 1101 OUT Token. USB Module performs an OUT (TX) transaction. IN Token. USB Module performs an In (RX) transaction. SETUP Token. USB Module performs a SETUP (TX) transaction This 4 bit field holds the Endpoint address for the token command. The four bit value written must be a valid endpoint.
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Memory Map/Register Definitions 42.4.21 BDT Page Register 2 (USBx_BDTPAGE2) The Buffer Descriptor Table Page Register 2 contains an 8-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Host mode control, bulk and interrupt transfers the EPHSHK bit should be set to 1. For Isochronous transfers it should be set to 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers.
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Memory Map/Register Definitions 42.4.24 USB Control Register (USBx_USBCTRL) Addresses: USB0_USBCTRL is 4007_2000h base + 100h offset = 4007_2100h Bit Read Write Reset 7 6 SUSP PDE 1 1 5 4 3 2 1 0 0 0 0 0 0 0 0 USBx_USBCTRL field descriptions Field 7 SUSP 6 PDE 5–0 Reserved Description Places the USB transceiver into the suspend state. 0 1 USB transceiver is not in suspend state. USB transceiver is in suspend state. Enables the weak pulldowns on the USB transceiver.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_OBSERVE field descriptions (continued) Field 5 Reserved 4 DMPD Description This read-only field is reserved and always has the value zero. Provides observability of the D- Pull Down signal output from the USB OTG module. 0 1 D- pulldown disabled. D- pulldown enabled. 3–1 Reserved This read-only field is reserved and always has the value zero. 0 Reserved This read-only field is reserved and always has the value zero. 42.4.
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Memory Map/Register Definitions 42.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0) Addresses: USB0_USBTRC0 is 4007_2000h base + 10Ch offset = 4007_210Ch Bit 7 6 5 4 3 Read 2 0 1 0 SYNC_DET USB_ RESUME_ INT 0 0 USBRESMEN Write USBRESET 1 Reset 0 0 0 0 0 0 USBx_USBTRC0 field descriptions Field 7 USBRESET Description USB reset Generates a hard reset to the USB_OTG module. After this bit is set and the reset occurs, this bit is automatically cleared.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.5 OTG and Host Mode Operation The Host Mode logic allows devices such as digital cameras and palmtop computers to function as a USB Host Controller. The OTG logic adds an interface to allow the OTG Host Negotiation and Session Request Protocols (HNP and SRP) to be implemented in software. Host Mode allows a peripheral such as a digital camera to be connected directly to a USB compliant printer.
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Host Mode Operation Examples 2. Enable the ATTACH interrupt (INT_ENB[ATTACH]=1). 3. Wait for ATTACH interrupt (INT_STAT[ATTACH]). Signaled by USB Target pullup resistor changing the state of DPLUS or DMINUS from 0 to 1 (SE0 to J or K state). 4. Check the state of the JSTATE and SE0 bits in the control register.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) complete. When the BDT is written a token done (INT_STAT[TOK_DNE]) interrupt is asserted. This completes the setup phase of the setup transaction. Refer to the Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework" (http://www.usb.org/developers/docs). 7.
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On-The-Go Operation 1. Complete all steps discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant. 2. Write the ENDPT0 to 0x1D register to enable transmit and receive transfers with handshaking enabled. 3. Setup the Even TX EP0 BDT to transfer up to 64 bytes. 4.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.7.1 OTG Dual Role A Device Operation A device is considered the A device because of the type of cable attached. If the USB Type A connector or the USB Type Mini A connector is plugged into the device, he is considered the A device. A dual role A device operates as the following flow diagram and state description table illustrates. A_IDLE B_IDLE A_WAIT_VFALL A_WAIT_VRISE A_PERIPHERAL A_WAIT_BCON A_SUSPEND A_HOST Figure 42-91.
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On-The-Go Operation Table 42-94. State Descriptions for the Dual Role A Device Flow (continued) State Action Response A_WAIT_BCON After 200 msec without Attach or ID Interrupt. (This could wait forever if desired.) Go to A_WAIT_FALL A_VBUS_VLD Interrupt and B device attaches Go to A_HOST Turn off DRV_VBUS Turn on Host Mode A_HOST Enumerate Device determine OTG Support.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) B_IDLE A_IDLE B_HOST B_WAIT_ACON B_SRP_INIT B_PERIPHERAL Figure 42-92. Dual Role B Device Flow Diagram Table 42-95. State Descriptions for the Dual Role B Device Flow State Action Response B_IDLE If ID\ Interrupt. Go to A_IDLE A Type A cable has been plugged in and the device should now respond as a Type A device. If B_SESS_VLD Interrupt. Go to B_PERIPHERAL The A device has turned on VBUS and begins a session.
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On-The-Go Operation K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1088 Freescale Semiconductor, Inc.
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Chapter 43 USB Device Charger Detection Module (USBDCD) 43.1 Preface 43.1.1 References The following publications are referenced in this document. For updates to these specifications, see http://www.usb.org. • USB Battery Charging Specification Revision 1.1, USB Implementers Forum • Universal Serial Bus Specification Revision 2.0, USB Implementers Forum 43.1.2 Acronyms and Abbreviations The following table contains acronyms and abbreviations used in this document. Table 43-1.
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Introduction Table 43-1. Acronyms and Abbreviated Terms (continued) Term Meaning OTG On-The-Go RDM_DWN D- pulldown resistance for data pin contact detect VDAT_REF Data detect reference voltage for the voltage comparator VDP_SRC Voltage source for the D+ line VLGC Threshold voltage for logic high 43.1.3 Glossary The following table shows a glossary of terms used in this document. Table 43-2.
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Chapter 43 USB Device Charger Detection Module (USBDCD) clk reset Digital Block Bus interface & registers Analog Block Timer Unit Voltage Comparator bus Control and Feedback state of D- Current Sink D+ D- state of D+ Analog Control Unit D- pulldown enable Current Source Voltage Source Figure 43-1. Block Diagram The USBDCD module consists of 2 main blocks: • A digital block provides the programming interface (memory-mapped registers) and includes the timer unit and the analog control unit.
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Module Signal Description Table 43-3. Module Modes and Their Conditions Module Mode Description Conditions When Used Enabled The module performs the charger detection sequence. System software should enable the module only when all of the following conditions are true: • The system uses a rechargeable battery. • The device is being used in an FS USB device application. • The device has detected that it is attached to the USB cable.
PAGE 1093
Chapter 43 USB Device Charger Detection Module (USBDCD) 43.3.1 USB Signal Descriptions The following table shows a summary of module signals that interface with the device's pins. Table 43-5. USB Signal Descriptions Signal Description I/O usb_dm USB D- analog data signal. The analog block interfaces directly to the Dsignal on the USB bus. I/O usb_dp USB D+ analog data signal. The analog block interfaces directly to the D+ signal on the USB bus. I/O avdd331 3.
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Memory Map/Register Definition USBDCD memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_5008 Status Register (USBDCD_STATUS) 32 R 0000_0000h 43.4.3/ 1096 4003_5010 TIMER0 Register (USBDCD_TIMER0) 32 R/W 0010_0000h 43.4.4/ 1098 4003_5014 USBDCD_TIMER1 32 R/W 000A_0028h 43.4.5/ 1099 4003_5018 USBDCD_TIMER2 32 R/W 0028_0001h 43.4.6/ 1099 43.4.
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Chapter 43 USB Device Charger Detection Module (USBDCD) USBDCD_CONTROL field descriptions (continued) Field Description Determines whether the charger detection sequence is initiated. 0b0 0b1 23–17 Reserved Do not start the sequence. Writes of this value have no effect. Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. This read-only field is reserved and always has the value zero.
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Memory Map/Register Definition USBDCD_CLOCK field descriptions Field Description 31–12 Reserved This read-only field is reserved and always has the value zero. 11–2 Numerical Value of Clock Speed in Binary CLOCK_SPEED The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to 1023 when clock unit is MHz and 4 to 1023 when clock unit is KHz.
PAGE 1097
Chapter 43 USB Device Charger Detection Module (USBDCD) USBDCD_STATUS field descriptions Field 31–23 Reserved 22 ACTIVE Description This read-only field is reserved and always has the value zero. Active Status Indicator Indicates whether the sequence is running. 0b0 0b1 21 TO Timeout Flag Indicates whether the detection sequence has passed the timeout threshhold. 0b0 0b1 20 ERR Indicates whether there is an error in the detection sequence. Indicates the status of the charger detection sequence.
PAGE 1098
Memory Map/Register Definition 43.4.4 TIMER0 Register (USBDCD_TIMER0) TIMER0 has an TSEQ_INIT field that represents the system latency (in ms) measured from the time VBUS goes active to the time system software initiates the charger detection sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT.
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Chapter 43 USB Device Charger Detection Module (USBDCD) 43.4.
PAGE 1100
Functional Description USBDCD_TIMER2 field descriptions (continued) Field Description 25–16 Time Period Before Enabling D+ Pullup TVDPSRC_CON Sets the amount of time (in ms) that the module waits after charging port detection before system software should enable the D+ pullup to connect to the USB host. Valid values are 1-1023, but the USB Battery Charging Specification requires a minimum value of 40 ms. 15–4 Reserved 3–0 CHECK_DM This read-only field is reserved and always has the value zero.
PAGE 1101
Chapter 43 USB Device Charger Detection Module (USBDCD) Table 43-13. USB Battery Charger Subsystem Components Component Battery Charger IC Description The external battery charger IC regulates the charge rate to the rechargable battery. System software is responsible for communicating the appropriate charge rates. Charger Maximum Current Drawn1 Standard host port up to 500 mA Charging host port up to 1500 mA Dedicated charging port up to 1800 mA 1.
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Functional Description 1 2 Initial VBUS Conditions Detect Charger Detection Phase 3 4 5 6 Data Pin Contact Detection Charging Port Detection Charger Type Detection Timeout T UNIT_CON_ELAPSED = T SEQ_INIT T UNIT_CON_ELAPSED =1s V B U S a t p o rta b le U S B d e v ice I DEV_DCHG D e d ic a te d C h a rg e r C h a rg in g H o s t T SEQ_INIT Dedicated Charger C h a rg in g H o s t I DEV_HCHG_LFS I SUSP 0m A I DP_SRC R DM_DWN FullSpeed Portable USB Device D+ on o ff TDCD_DBNC lgc_hi lgc_
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Chapter 43 USB Device Charger Detection Module (USBDCD) Table 43-14. Overview of the Charger Detection Sequence Phase Overview Description Full Description 1 Initial Conditions Initial system conditions that need to be met before initiating the detection sequence Initial System Conditions 2 VBUS Detection System software detects contact of the VBUS signal with the system interrupt pin VBUS_detect.
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Functional Description • recently plugged into a USB port, and • drawing no more than 2.5 mA total system current from the USB bus. There are many allowable precursors to this set of initial conditions. For example, the device could have been powered down and subsequently powered up upon being plugged into the USB bus. Alternatively, the device could have been in a low power state that was exited due to the plugin event.
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Chapter 43 USB Device Charger Detection Module (USBDCD) Plug Receptacle VBUS VBUS D D D+ D+ GND GND Figure 43-10. Relative Pin Positions in USB Plugs and Receptacles As a result, when a portable USB device is attached to an upstream port, the portable USB device detects VBUS before the data pins have made contact. The time between power pins and data pins making contact depends on how fast the plug is inserted into the receptable. Delays of several hundred milliseconds are possible. 43.5.1.3.
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Functional Description • updates the STATUS register to reflect phase completion (See Table 43-18 for field values.) • directly proceeds to the next step in the sequence: detection of a charging port See Charging Port Detection. 43.5.1.4 Charging Port Detection Once it is known that the data pins have made contact, the module waits for a fixed delay of 1 ms, and then attempts to detect if it has been plugged into a charging port.
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Chapter 43 USB Device Charger Detection Module (USBDCD) • Sets the CONTROL[IF] bit. • Generates an interrupt if enabled (the CONTROL[IE] bit is set). At this point, control has been passed to system software via the interrupt. The rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1. Read the STATUS register. 2. Set the CONTROL[IACK] bit to acknowledge the interrupt. 3. Set the CONTROL[SR] bit to issue a software reset to the module. 4. Disable the module. 5.
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Functional Description • Updates the STATUS register to reflect the error with SEQ_RES = 00. (See Table 43-18 for field values.) • Sets the CONTROL[IF] bit. • Generates an interrupt if enabled (the CONTROL[IE] bit is set). Note that in this case the module does not wait for the TVDPSRC_CON interval to elapse. At this point, control has been passed to system software via the interrupt. The rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1.
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Chapter 43 USB Device Charger Detection Module (USBDCD) • Updates the STATUS register to reflect that a dedicated charger has been detected with SEQ_RES = 11. (See Table 43-18 for field values.) • Sets the CONTROL[IF] bit. • Generates an interrupt if enabled (the CONTROL[IE] bit is set). At this point, control has been passed to system software via the interrupt. Software should: 1. Read the STATUS register. 2.
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Functional Description 43.5.1.6 Charger Detection Sequence Timeout The maximum time to connect allowed under the USB Battery Charging Specification, v1.1 is one second. If the Unit Connection Timer reaches the one second limit and the sequence is still running (indicated by the STATUS[ACTIVE] bit still being set), the module does the following: • Updates the STATUS register to reflect that a timeout error has occured. (See Table 43-18 for field values.) • Sets the CONTROL[IF] bit.
PAGE 1111
Chapter 43 USB Device Charger Detection Module (USBDCD) Note that the TUNITCON register field will stop incrementing when it reaches its maximum value so it will not rollover to zero and start counting up again. 43.5.2 Interrupts and Events The USBDCD module has an interrupt to alert system software of certain events, which are listed in the following table. All events except the Phase Complete event for the Data Pin Detection phase can trigger an interrupt. Table 43-18.
PAGE 1112
Functional Description An interrupt is generated only if the CONTROL[IE] bit is set. The CONTROL[IF] bit is always set under interrupt conditions, even if the IE bit is cleared. In this case, software can poll the IF flag to determine if an interrupt condition is pending. Writes to the IF bit are ignored. To reset the IF bit, set the CONTROL[IACK] bit to acknowledge the interrupt.Writing to the IACK bit while the IF bit is cleared has no effect. 43.5.
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Chapter 43 USB Device Charger Detection Module (USBDCD) A software reset also returns all internal logic, timers, and counters to their reset states. State Machines return to IDLE. If the module is already active (STATUS[ACTIVE] = 1), a software reset stops the sequence. Note Software should always initiate a software reset before starting the sequence (setting the CONTROL[START] bit) to ensure the module is in a known state. 43.
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Application Information The USBDCD module is compatible with systems that do not check the strength of the battery. Therefore, this module assumes that the battery is good, so the USB device must immediately connect to the USB bus by pulling the D+ line high after the USBDCD module has determined that the device is attached to a charging port. The module is also compatible with systems that do check the strength of the battery.
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Chapter 44 USB Voltage Regulator 44.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel. When the input power supply is below 3.6 V, the regulator goes to passthrough mode.
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Introduction 44.1.1 Overview A simplified block diagram for the USB Voltage Regulator module is shown below. STANDBY Regulator Yes No Other Modules STANDBY Power Supply reg33_in Regulated Output Voltage reg33_out RUN Regulator ESR: 5m -> 100m Ohms Voltage Regulator External Capacitor typical = 2.2uF Chip Figure 44-2. USB Voltage Regulator Block Diagram This module uses 2 regulators in parallel.
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Chapter 44 USB Voltage Regulator • Automatic current limiting if the load current is greater than 290 mA. • Automatic power-up once some voltage is applied to the regulator input. • Pass-through mode for regulator input voltages less than 3.6 V • Small output capacitor: 2.2 uF • Stable with aluminum, tantalum or ceramic capacitors. 44.1.
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USB Voltage Regulator Module Signal Descriptions K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1118 Freescale Semiconductor, Inc.
PAGE 1119
Chapter 45 CAN (FlexCAN) 45.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification.
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Introduction Peripheral Bus Interface Address, Data, Clocks, Interrupts Registers Message Buffers (MBs) CAN Control Host Interface Tx Arbitration Rx Matching RAM CAN Protocol Engine CAN Tx CAN Rx Chip CAN Bus Figure 45-1. FlexCAN Block Diagram 45.1.
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Chapter 45 CAN (FlexCAN) 45.1.2 FlexCAN Module Features The FlexCAN module includes these distinctive legacy features: • Full Implementation of the CAN protocol specification, Version 2.
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Introduction • Short latency time due to an arbitration scheme for high-priority messages • Low power modes, with programmable wake up on bus activity Furthermore, the new major features below are also provided in addition to the previous FlexCAN version: • Remote request frames may be handled automatically or by software • Safe mechanism for ID Filter configuration in Normal Mode • CAN bit time settings and configuration bits can only be written in "Freeze" mode • Tx mailbox status (Lowest priority buffer
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Chapter 45 CAN (FlexCAN) It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze Mode is entered when the HALT bit in MCR is set or when Debug Mode is requested at MCU level and the FRZ_ACK bit in the MCR Register is asserted by the FlexCAN. In this mode, no transmission or reception of frames is done and synchronicity to the CAN bus is lost. See Freeze Mode for more information.
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FlexCAN Signal Descriptions This low power mode is entered when Stop Mode is requested at MCU level and the LPM_ACK bit in the MCR Register is asserted by the FlexCAN. When in Stop Mode, the module puts itself in an inactive state and then informs the CPU that the clocks can be shut down globally. Exit from this mode happens when the Stop Mode request is removed or when activity is detected on the CAN bus and the Self Wake Up mechanism is enabled. See Stop Mode for more information. 45.
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Chapter 45 CAN (FlexCAN) The complete memory map for a FlexCAN module is shown in the following table. The address space occupied by FlexCAN has 128 bytes for registers starting at the module base address, followed by embedded RAM starting at address 0x0080. Each individual register is identified by its complete name and the corresponding mnemonic. The access type can be Supervisor (S) or Unrestricted (U).
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Memory Map/Register Definition The FlexCAN module can store CAN messages for transmission and reception using Mailboxes and Rx FIFO structures. This module's memory map includes sixteen 128-bit message buffers (MBs) that occupy the range from offset 0x80 to 0x17F. CAN memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_4000 Module Configuration Register (CAN0_MCR) 32 R/W D890_000Fh 45.3.
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Chapter 45 CAN (FlexCAN) CAN memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_4880 Rx Individual Mask Registers (CAN0_RXIMR0) 32 R/W Undefined 45.3.19/ 1159 4002_4884 Rx Individual Mask Registers (CAN0_RXIMR1) 32 R/W Undefined 45.3.19/ 1159 4002_4888 Rx Individual Mask Registers (CAN0_RXIMR2) 32 R/W Undefined 45.3.19/ 1159 4002_488C Rx Individual Mask Registers (CAN0_RXIMR3) 32 R/W Undefined 45.3.
PAGE 1128
Memory Map/Register Definition CAN memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400A_4014 Rx 14 Mask Register (CAN1_RX14MASK) 32 R/W FFFF_ FFFFh 45.3.6/ 1140 400A_4018 Rx 15 Mask Register (CAN1_RX15MASK) 32 R/W FFFF_ FFFFh 45.3.7/ 1141 400A_401C Error Counter (CAN1_ECR) 32 R/W 0000_0000h 45.3.8/ 1142 400A_4020 Error and Status 1 Register (CAN1_ESR1) 32 R/W 0000_0000h 45.3.
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Chapter 45 CAN (FlexCAN) CAN memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400A_489C Rx Individual Mask Registers (CAN1_RXIMR7) 32 R/W Undefined 45.3.19/ 1159 400A_48A0 Rx Individual Mask Registers (CAN1_RXIMR8) 32 R/W Undefined 45.3.19/ 1159 400A_48A4 Rx Individual Mask Registers (CAN1_RXIMR9) 32 R/W Undefined 45.3.19/ 1159 400A_48A8 Rx Individual Mask Registers (CAN1_RXIMR10) 32 R/W Undefined 45.3.
PAGE 1130
Memory Map/Register Definition 45.3.2 Module Configuration Register (CANx_MCR) This register defines global system configurations, such as the module operation modes and the maximum message buffer configuration.
PAGE 1131
Chapter 45 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used as Rx FIFO ID Filter Table elements.
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Memory Map/Register Definition CANx_MCR field descriptions (continued) Field Description Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered Freeze Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN prescaler is running again. If Freeze Mode is requested while FlexCAN is in a low power mode, then the FRZACK bit will only be set when the low power mode is exited. See Section "Freeze Mode".
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Chapter 45 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description NOTE: LPMACK will be asserted within 180 CAN bits from the low power mode request by the CPU, and negated within 2 CAN bits after the low power mode request removal (see Section "Protocol Timing"). 0 1 19 Reserved 18 DOZE This field is reserved. Doze Mode Enable This bit defines whether FlexCAN is allowed to enter low power mode when Doze Mode is requested at MCU level.
PAGE 1134
Memory Map/Register Definition CANx_MCR field descriptions (continued) Field Description frame is sent in the CAN bus without notification. This bit can only be written in Freeze mode as it is blocked by hardware in other modes. NOTE: When MCR[AEN] is asserted, only the abort mechanism (see Section "Transmission Abort Mechanism") must be used for updating Mailboxes configured for transmission. CAUTION: Writing the Abort code into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is asserted.
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Chapter 45 CAN (FlexCAN) 45.3.3 Control 1 Register (CANx_CTRL1) This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop Back Mode, Listen-Only Mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the clock prescaler.
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Memory Map/Register Definition CANx_CTRL1 field descriptions (continued) Field Description This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable values are 1–7. This field can only be written in Freeze mode as it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta. 15 BOFFMSK Bus Off Mask This bit provides a mask for the Bus Off Interrupt. 0 1 14 ERRMSK Error Mask This bit provides a mask for the Error Interrupt.
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Chapter 45 CAN (FlexCAN) CANx_CTRL1 field descriptions (continued) Field Description This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can only be written if MCR[WRNEN] bit is asserted. 0 1 9–8 Reserved 7 SMP This read-only field is reserved and always has the value zero. CAN Bit Sampling This bit defines the sampling mode of CAN bits at the Rx input.
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Memory Map/Register Definition CANx_CTRL1 field descriptions (continued) Field Description This bit configures FlexCAN to operate in Listen-Only Mode. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message.
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Chapter 45 CAN (FlexCAN) Addresses: CAN0_TIMER is 4002_4000h base + 8h offset = 4002_4008h CAN1_TIMER is 400A_4000h base + 8h offset = 400A_4008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMER W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANx_TIMER field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value z
PAGE 1140
Memory Map/Register Definition CANx_RXMGMASK field descriptions (continued) Field Description These bits mask the Mailbox filter bits. Note that the alignment with the ID word of the Mailbox is not perfect as the two most significant MG bits affect the fields RTR and IDE, which are located in the Control and Status word of the Mailbox. The following table shows in detail which MG bits mask each Mailbox filter field.
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Chapter 45 CAN (FlexCAN) CANx_RX14MASK field descriptions Field Description 31–0 RX14M[31:0] Rx Buffer 14 Mask Bits Each mask bit masks the corresponding Mailbox 14 filter field in the same way that RXMGMASK masks other Mailboxes' filters. See the description of the CAN_RXMGMASK register. 0 1 The corresponding bit in the filter is "don’t care." The corresponding bit in the filter is checked. 45.3.7 Rx 15 Mask Register (CANx_RX15MASK) This register is located in RAM.
PAGE 1142
Memory Map/Register Definition 45.3.8 Error Counter (CANx_ECR) This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter (RXERRCNT field). The rules for increasing and decreasing these counters are described in the CAN protocol and are completely implemented in the FlexCAN module. Both counters are read-only except in Freeze Mode, where they can be written by the CPU.
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Chapter 45 CAN (FlexCAN) Addresses: CAN0_ECR is 4002_4000h base + 1Ch offset = 4002_401Ch CAN1_ECR is 400A_4000h base + 1Ch offset = 400A_401Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 0 R 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 RXERRCNT W Reset 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 TXERRCNT 0 0 0 0 0 0 0 0 CANx_ECR field descriptions Field 31–16 Reserved Description This read-only field is reserved and always has the v
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Memory Map/Register Definition Addresses: CAN0_ESR1 is 4002_4000h base + 20h offset = 4002_4020h CAN1_ESR1 is 400A_4000h base + 20h offset = 400A_4020h 29 28 27 26 25 24 23 22 21 20 19 0 R 18 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CRCERR FRMERR STFERR TXWRN RXWRN IDLE TX FLTCONF RX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKINT 0 ERRINT 0 BOFFINT Reset ACKERR w1c BIT0ERR w1c BIT1ERR W 17 RWRNINT
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Chapter 45 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description Otherwise it will be set when the WRNEN is set again. Writing ‘0’ has no effect. This bit is not updated during Freeze mode. 0 1 15 BIT1ERR No such occurrence The Rx error counter transitioned from less than 96 to greater than or equal to 96. Bit1 Error This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
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Memory Map/Register Definition CANx_ESR1 field descriptions (continued) Field Description This bit indicates when repetitive errors are occurring during message transmission. This bit is not updated during Freeze mode. 0 1 8 RXWRN Rx Error Warning This bit indicates when repetitive errors are occurring during message reception. This bit is not updated during Freeze mode. 0 1 7 IDLE No such occurrence CAN bus is now IDLE. FlexCAN in Transmission This bit indicates if FlexCAN is transmitting a message.
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Chapter 45 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description 0 1 1 ERRINT No such occurrence FlexCAN module entered ‘Bus Off’ state Error Interrupt This bit indicates that at least one of the Error Bits (bits 15-10) is set. If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect.
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Memory Map/Register Definition CANx_IMASK2 field descriptions (continued) Field Description 0 1 The corresponding buffer Interrupt is disabled. The corresponding buffer Interrupt is enabled. 45.3.11 Interrupt Masks 1 Register (CANx_IMASK1) This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception (i.e.
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Chapter 45 CAN (FlexCAN) Addresses: CAN0_IFLAG2 is 4002_4000h base + 2Ch offset = 4002_402Ch CAN1_IFLAG2 is 400A_4000h base + 2Ch offset = 400A_402Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R BUFHI W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANx_IFLAG2 field descriptions Field 31–0 BUFHI Description Buffer MBi Interrupt Each bit flags the corresponding Fle
PAGE 1150
Memory Map/Register Definition Addresses: CAN0_IFLAG1 is 4002_4000h base + 30h offset = 4002_4030h CAN1_IFLAG1 is 400A_4000h base + 30h offset = 400A_4030h Bit 31 30 29 28 27 26 25 24 23 R BUF31TO8I[bit 8] W w1c 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R BUF31TO8I[7:0] BUF5I 0 BUF6I 0 BUF7I Reset BUF4TO0I W w1c w1c w1c w1c w1c 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 CANx_IFLAG1
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Chapter 45 CAN (FlexCAN) CANx_IFLAG1 field descriptions (continued) Field Description 0 1 5 BUF5I No occurrence of MB6 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO almost full (when MCR[RFEN]=1) MB6 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO almost full (when MCR[RFEN]=1) Buffer MB5 Interrupt or "Frames available in Rx FIFO" When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB5.
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Memory Map/Register Definition 45.3.14 Control 2 Register (CANx_CTRL2) This register contains control bits for CAN errors, FIFO features, and mode selection.
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Chapter 45 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN x 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the SETUP_MB value (memory space available) the exceeding ones will not be functional.
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Memory Map/Register Definition CANx_CTRL2 field descriptions (continued) Field Description If TASD is 0 then the arbitration start is not delayed, thus the CPU has less time to configure a Tx MB for the next arbitration, but more time is reserved for arbitration. In the other hand, if TASD is 24 then the CPU can configure a Tx MB later and less time is reserved for arbitration.
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Chapter 45 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description 0 1 15–0 Reserved Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits. Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. This read-only field is reserved and always has the value zero. 1.
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Memory Map/Register Definition CANx_ESR2 field descriptions (continued) Field Description already been scanned (i.e. it is behind Tx Arbitration Pointer) during the Tx arbitration process. If there is no inactive Mailbox and only one Tx Mailbox which is being transmitted then VPS is not asserted. VPS is negated upon the start of every Tx arbitration process or upon a write to Control and Status word of any Mailbox.
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Chapter 45 CAN (FlexCAN) CANx_CRCR field descriptions (continued) Field Description 22–16 MBCRC CRC Mailbox This field indicates the number of the Mailbox corresponding to the value in TXCRC field. 15 Reserved This read-only field is reserved and always has the value zero. 14–0 TXCRC CRC Transmitted This field indicates the CRC value of the last message transmitted. This field is updated at the same time the Tx Interrupt Flag is asserted. 45.3.
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Memory Map/Register Definition CANx_RXFGMASK field descriptions (continued) Field Description Rx FIFO ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter Fields RTR IDE RXIDA A FGM[31] FGM[30] FGM[29:1] B FGM[31], FGM[15] FGM[30], FGM[14] C - - RXIDB1 RXIDC2 - - Reserved FGM[0] FGM[29:16], FGM[13:0] - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0] 1.
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Chapter 45 CAN (FlexCAN) CANx_RXFIR field descriptions Field Description 31–9 Reserved This read-only field is reserved and always has the value zero. 8–0 IDHIT Identifier Acceptance Filter Hit Indicator This field indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Rx FIFO. If multiple filters match the incoming message ID then the first matching IDAF found (lowest number) by the matching process is indicated.
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Memory Map/Register Definition CANx_RXIMRn field descriptions (continued) Field Description For Rx FIFO ID Filter Table elements, see the RXFGMASK register description. 0 1 The corresponding bit in the filter is "don't care." The corresponding bit in the filter is checked. 45.3.56 Message Buffer Structure The Message Buffer structure used by the FlexCAN module is represented in the following figure.
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Chapter 45 CAN (FlexCAN) Table 45-109. Message Buffer Code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment 0b0100: EMPTY MB is active and empty. EMPTY - FULL - When a frame is received successfully (after move-in process. Refer to Section "Move-in" for details), the CODE field is automatically updated to FULL. 0b0010: FULL MB is full.
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Memory Map/Register Definition Table 45-109. Message Buffer Code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment 0b0110: OVERRUN - MB is being overwritten into a full buffer. OVERRUN Yes FULL - If the CODE field indicates OVERRUN and CPU has serviced the MB, when a new frame is moved to the MB, the code returns to FULL.
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Chapter 45 CAN (FlexCAN) Table 45-109. Message Buffer Code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment 0b1010: RANSWER4 - A frame was configured to recognize a Remote Request Frame and transmit a Response Frame in return. RANSWER - TANSWER(0b111 0) 0 A Remote Answer was configured to recognize a remote request frame received, after that a MB is set to transmit a response frame.
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Memory Map/Register Definition Table 45-110. Message Buffer Code for Tx buffers CODE Description Tx Code BEFORE tx frame MBRTR Tx Code AFTER successful transmission Comment 0b1000: INACTIVE MB is not active INACTIVE - - MB does not participate in the arbitration process. 0b1001: ABORT - MB is aborted ABORT - - MB does not participate in the arbitration process. 0b1100: DATA - MB is a Tx Data Frame (MB RTR must be 0) DATA 0 INACTIVE Transmit data frame unconditionally once.
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Chapter 45 CAN (FlexCAN) Fixed recessive bit, used only in extended format. It must be set to '1' by the user for transmission (Tx Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is interpreted as arbitration loss.
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Memory Map/Register Definition This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx mailboxes. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. See Arbitration process. ID — Frame Identifier In Standard Frame format, only the 11 most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored.
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Chapter 45 CAN (FlexCAN) An additional memory area, that starts at 0xE0 and may extend up to 0x2DC (normally occupied by MBs 6 up to 37) depending on the CTRL2[RFFN] field setting, contains the ID Filter Table (configurable from 8 to 128 table elements) that specifies filtering criteria for accepting frames into the FIFO.
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Memory Map/Register Definition Table 45-113. ID Table structure (continued) B C RTR IDE RXIDB_0 (Standard = 29-19, Extended = 29-16) RTR IDE RXIDB_1 (Standard = 13-3, Extended = 13-0) RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 (Std/Ext = 31-24) (Std/Ext = 23-16) (Std/Ext = 15-8) (Std/Ext = 7-0) = Unimplemented or Reserved RTR — Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID.
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Chapter 45 CAN (FlexCAN) 45.4 Functional Description The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of up to 64Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Message Buffer Structure).
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Functional Description 3. Write the ID word. 4. Write the data bytes. 5. Write the DLC, Control and CODE fields of the Control and Status word to activate the MB. Once the MB is activated in the fourth step, it will participate into the arbitration process and eventually be transmitted according to its priority.
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Chapter 45 CAN (FlexCAN) • When FlexCAN exits Bus Off state. • Upon leaving Freeze Mode or Low Power Mode. If the arbitration process does not manage to evaluate all Mailboxes before the CAN bus has reached the first bit of the Intermission field the temporary arbitration winner is invalidated and the FlexCAN will not compete for the CAN bus in the next opportunity.
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Functional Description Table 45-114. Composition of the arbitration value when Local Priority is disabled Format Mailbox Arbitration Value (32 bits) Standard (IDE = 0) Standard ID (11 bits) Extended (IDE = 1) Extended ID[28:18] (11 bits) 45.4.2.2.2 RTR (1 bit) IDE (1 bit) - (18 bits) - (1 bit) SRR (1 bit) IDE (1 bit) Extended ID[17:0] (18 bits) RTR (1 bit) Local Priority enabled If Local Priority is desired MCR[LPRIO_EN] must be asserted.
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Chapter 45 CAN (FlexCAN) Arbitration process can be triggered in the following situations: • During Rx and Tx frames from CAN CRC field to end of frame. Arbitration start point depends on instantiation parameters NUMBER_OF_MB and TASD. Additionally, TASD value may be changed to optimize the arbitration start point. • During CAN BusOff state from TX_ERR_CNT=124 to 128. Arbitration start point depends on instantiation parameters NUMBER_OF_MB and TASD.
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Functional Description • If C/S write is performed in the arbitration winner, a new process is restarted immediately. • If C/S write is performed in a MB whose number is higher than the Tx arbitration pointer, the ongoing arbitration process will scan this MB as normal. 45.4.3 Receive Process To be able to receive CAN frames into a Mailbox, the CPU must prepare it for reception by executing the following steps: 1.
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Chapter 45 CAN (FlexCAN) 3. Read the contents of the Mailbox. Once Mailbox is locked now, its contents won’t be modified by FlexCAN Move-in processes. See Section "Move-in". 4. Acknowledge the proper flag at IFLAG registers. 5. Read the Free Running Timer. It is optional but recommended to unlock Mailbox as soon as possible and make it available for reception.
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Functional Description 5. Clear the Frames Available in Rx FIFO interrupt by writing 1 to IFLAG[BUF5I] bit (mandatory – releases the MB and allows the CPU to read the next Rx FIFO entry) 45.4.4 Matching Process The matching process scans the MB memory looking for Rx MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the priority of scanning can be selected between Mailboxes and FIFO filters.
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Chapter 45 CAN (FlexCAN) Table 45-116.
PAGE 1178
Functional Description If the selected priority is Rx FIFO first: • if the Rx FIFO is a matched structure and is free-to-receive then the Rx FIFO is the matching winner regardless of the scan for Mailboxes; • otherwise (the Rx FIFO is not a matched structure or is not free-to-receive), then the matching winner is searched among Mailboxes as described above.
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Chapter 45 CAN (FlexCAN) Table 45-117.
PAGE 1180
Functional Description Suppose, for example, that the FIFO is disabled, IRMQ is enabled and there are two MBs with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array. When the first message arrives, the matching algorithm will find the first match in MB number 2. The code of this MB is EMPTY, so the message is stored there.
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Chapter 45 CAN (FlexCAN) but only one is performed at a given time as described ahead.
PAGE 1182
Functional Description The move-in process is not atomic, in such a way that it is immediately cancelled by the inactivation of the destination Mailbox (see Section "Message Buffer Inactivation") and in this case the Mailbox may be left partially updated, thus incoherent. The exception is if the move-in destination is an Rx FIFO Message Buffer, then the process cannot be cancelled.
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Chapter 45 CAN (FlexCAN) • MCR[AEN] bit must be asserted; • the first CPU action must be the writing of abort code (0b1001) into the CODE field of the Control and Status word. The active MBs configured as transmission must be aborted first and then they may be updated.
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Functional Description • CPU reads the CODE field to check if the frame was either transmitted (CODE=0b1000) or aborted (CODE=0b1001). • It is necessary to clear the corresponding IFLAG in order to allow the MB to be reconfigured. 45.4.6.2 Message Buffer Inactivation Inactivation is a mechanism provided to protect the Mailbox against updates by the FlexCAN internal processes, thus allowing the CPU to rely on Mailbox data coherence after having updated it, even in Normal Mode.
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Chapter 45 CAN (FlexCAN) FlexCAN. CPU must maintain data coherency in the FIFO region when RFEN is asserted. 45.4.6.3 Message Buffer Lock Mechanism Besides MB inactivation, FlexCAN has another data coherence mechanism for the receive process. When the CPU reads the Control and Status word of an Rx MB with codes FULL or OVERRUN, FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.
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Functional Description Inactivation takes precedence over locking. If the CPU inactivates a locked Rx MB, then its lock status is negated and the MB is marked as invalid for the current matching round. Any pending message on the SMB will not be transferred anymore to the MB. An MB is unlocked when the CPU reads the Free Running Timer Register (see Section "Free Running Timer Register (TIMER)"), or the C/S word of another MB.
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Chapter 45 CAN (FlexCAN) Clearing one of those three flags does not affect the state of the other two. An interrupt is generated if an IFLAG bit is asserted and the corresponding mask bit is asserted too. A powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load.
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Functional Description 45.4.8.1 Remote Frames Remote frame is a special kind of frame. The user can program a mailbox to be a Remote Request Frame by writing the mailbox as Transmit with the RTR bit set to '1'. After the remote request frame is transmitted successfully, the mailbox becomes a Receive Message Buffer, with the same ID as before.
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Chapter 45 CAN (FlexCAN) • Detection of a dominant bit in the first/second bit of Intermission • Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames) • Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload Frame Delimiter 45.4.8.
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Functional Description The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the 'time quantum' used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. f CANCLK f Tq = (Prescaler Value) A bit time is subdivided into three segments2 (reference Figure 45-105 and Table 45-118): • SYNC_SEG: This segment has a fixed length of one time quantum.
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Chapter 45 CAN (FlexCAN) Whenever CAN bit is used as a measure of duration (e.g.
PAGE 1192
Functional Description Note It is the user's responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module. 45.4.8.5 Arbitration and Matching Timing During normal reception and transmission of frames, the matching, arbitration, move-in and move-out processes are executed during certain time windows inside the CAN frame, as shown in the following figures.
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Chapter 45 CAN (FlexCAN) concurrent memory access due to the CPU or other internal peripheral. When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during the available time slot. In order to have sufficient time to do that, the following requirements must be observed: • A valid CAN bit timing must be programmed, as indicated in Table 45-119 • The peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e.
PAGE 1194
Functional Description As an example, taking the case of 64 MBs, if the oscillator and peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 45.4.
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Chapter 45 CAN (FlexCAN) • Grants write access to the Error Counters Register, which is read-only in other modes • Sets the NOT_RDY and FRZ_ACK bits in MCR After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before executing any other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all memory mapped registers are accessible, except for CTRL1[CLK_SRC] bit that can be read but cannot be written.
PAGE 1196
Functional Description The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and the reserved words within RAM may not be accessed when the module is in Disable Mode.
PAGE 1197
Chapter 45 CAN (FlexCAN) • CPU removing the Doze Mode request • CPU negating the DOZE bit of the MCR Register • Self Wake mechanism In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time FlexCAN entered Doze Mode, then upon detection of a recessive to dominant transition on the CAN bus, FlexCAN negates the DOZE bit, requests to resume its clocks and negates the LPM_ACK after the CAN protocol engine recognizes the negation of the Doze Mode request.
PAGE 1198
Functional Description • Waits for all internal activities like arbitration, matching, move-in and move-out to finish. A pending move-in is not taken into account.
PAGE 1199
Chapter 45 CAN (FlexCAN) 45.4.10 Interrupts Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG Registers.
PAGE 1200
Initialization/Application Information • Write access to positions whose bits are all currently read-only results in access error. If at least one of the bits is not read-only then no access error is issued. Write permission to positions or some of their bits can change depending on the mode of operation or transitory state. Refer to register and bit descriptions for details. • Read and write access to unimplemented address space results in access error.
PAGE 1201
Chapter 45 CAN (FlexCAN) Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low power mode should be exited and the clocks resumed before applying soft reset.
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Initialization/Application Information • If Rx FIFO was enabled, the ID filter table must be initialized • Other entries in each Message Buffer should be initialized as required • Initialize the Rx Individual Mask Registers • Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up interrupt • Negate the HALT bit in MCR Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
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Chapter 46 SPI (DSPI) 46.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The serial peripheral interface module provides a synchronous serial bus for communication between an MCU and an external peripheral device. 46.1.1 Block Diagram The block diagram of this module is as follows: K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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Introduction INTC eDMA Slave Bus Interface Clock/Reset SPI DMA and Interrupt Control POPR TX FIFO RX FIFO PUSHR CMD Data Data 32 32 SOUT Shift Register SIN SCK S PI Baud Rate, Delay & Transfer Control PCS[x]/SS/PCSS 8 Figure 46-1. DSPI Block Diagram 46.1.
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Chapter 46 SPI (DSPI) • 2 transfer attribute registers • Serial clock with programmable polarity and phase • Various programmable delays • Programmable serial frame size of 4 to 16 bits, expandable by software control • SPI frames longer than 16 bits can be supported using the continuous selection format.
PAGE 1206
Introduction 46.1.3.1 SPI Configuration The SPI configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI to operate as a basic SPI block with internal FIFOs supporting external queues operation. Transmit data and received data reside in separate FIFOs. The host CPU or a DMA controller read the received data from the receive FIFO and write transmit data to the transmit FIFO. For queued operations the SPI queues can reside in system RAM, external to the DSPI.
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Chapter 46 SPI (DSPI) • External stop mode • Debug mode The DSPI enters module-specific modes when the host writes a DSPI register. The MCUspecific modes are controlled by signals, external to the DSPI. The MCU-specific modes are modes that an MCU may enter in parallel to the DSPI block-specific modes. 46.1.4.1 Master Mode Master mode allows the DSPI to initiate and control serial communication. In this mode, the SCK signal and the PCS[x] signals are controlled by the DSPI and configured as outputs. 46.
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DSPI Signal Descriptions 46.1.4.5 Debug Mode Debug mode is used for system development and debugging. The MCR[FRZ] bit controls DSPI behavior in the debug mode. If the bit is set, the DSPI stops all serial transfers, when the MCU is in debug mode. If the bit is cleared, the MCU debug mode has no effect on the DSPI. 46.2 DSPI Signal Descriptions This section provides the DSPI signals description. The following table lists the signals that may connect off chip depending on device implementation. Table 46-1.
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Chapter 46 SPI (DSPI) 46.2.2 PCS1 - PCS3 — Peripheral Chip Selects 1 - 3 PCS1 - PCS3 are Peripheral Chip Select output signals in master mode. In slave mode, these signals are unused. 46.2.3 PCS4 — Peripheral Chip Select 4 In master mode, PCS4 is a Peripheral Chip Select output signal. In slave mode, this signal is unused. 46.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe PCS5 is a Peripheral Chip Select output signal.
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Memory Map/Register Definition 46.3 Memory Map/Register Definition Register accesses to memory addresses that are reserved or undefined result in a transfer error. Write access to the POPR register also results in a transfer error. SPI memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_C000 DSPI Module Configuration Register (SPI0_MCR) 32 R/W 0000_4001h 46.3.1/ 1212 4002_C008 DSPI Transfer Count Register (SPI0_TCR) 32 R/W 0000_0000h 46.3.
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Chapter 46 SPI (DSPI) SPI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_C084 DSPI Receive FIFO Registers (SPI0_RXFR2) 32 R 0000_0000h 46.3.11/ 1230 4002_C088 DSPI Receive FIFO Registers (SPI0_RXFR3) 32 R 0000_0000h 46.3.11/ 1230 4002_D000 DSPI Module Configuration Register (SPI1_MCR) 32 R/W 0000_4001h 46.3.1/ 1212 4002_D008 DSPI Transfer Count Register (SPI1_TCR) 32 R/W 0000_0000h 46.3.
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Memory Map/Register Definition 46.3.1 DSPI Module Configuration Register (SPIx_MCR) Contains bits to configure various attributes associated with DSPI operations. The HALT and MDIS bits can be changed at any time, but they only take effect on the next frame boundary. Only the HALT and MDIS bits in the MCR can be changed, while the DSPI is in the Running state.
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Chapter 46 SPI (DSPI) SPIx_MCR field descriptions (continued) Field Description Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug mode. 0 1 26 MTFE Modified Timing Format Enable Enables a modified transfer format to be used. 0 1 25 PCSSE Enables the PCS[5]/ PCSS to operate as a PCS Strobe output signal. 21–16 PCSIS[5:0] In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwrite existing data.
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Memory Map/Register Definition SPIx_MCR field descriptions (continued) Field Description When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. This bit can only be written when the MDIS bit is cleared. 0 1 12 DIS_RXF Disable Receive FIFO When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. This bit can only be written when the MDIS bit is cleared. 0 1 11 CLR_TXF Flushes the TX FIFO.
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Chapter 46 SPI (DSPI) 46.3.2 DSPI Transfer Count Register (SPIx_TCR) TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. Do not write the TCR when the DSPI is in the Running state.
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Memory Map/Register Definition Addresses: SPI0_CTAR0 is 4002_C000h base + Ch offset = 4002_C00Ch SPI0_CTAR1 is 4002_C000h base + 10h offset = 4002_C010h SPI1_CTAR0 is 4002_D000h base + Ch offset = 4002_D00Ch SPI1_CTAR1 is 4002_D000h base + 10h offset = 4002_D010h Bit 31 30 29 28 27 26 25 24 23 PCSSCK 19 18 17 16 LSBFE 20 CPHA 21 CPOL R 22 Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DBR FMSZ W PASC PDT PBR
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Chapter 46 SPI (DSPI) SPIx_CTARn field descriptions (continued) Field Description The number of bits transferred per frame is equal to the FMSZ field value plus 1. The minimum valid FMSZ field value is 3. 26 CPOL Clock Polarity Selects the inactive state of the Serial Communications Clock (SCK). This bit is used in both master and slave mode. For successful communication between serial devices, the devices must have identical clock polarities.
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Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field Description See the DT field description for details on how to compute the Delay after Transfer. Refer Delay after Transfer (tDT) for more details. 00 01 10 11 17–16 PBR Baud Rate Prescaler Selects the prescaler value for the baud rate. This field is used only in master mode. The baud rate is the frequency of the SCK. The system clock is divided by the prescaler value before the baud rate selection takes place.
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Chapter 46 SPI (DSPI) SPIx_CTARn field descriptions (continued) Field Description Table 46-33. Delay Scaler Encoding (continued) Field Value Delay Scaler Value 1111 65536 Refer PCS to SCK Delay (tCSC) for more details. 11–8 ASC After SCK Delay Scaler Selects the scaler value for the After SCK Delay. This field is used only in master mode. The After SCK Delay is the delay between the last edge of SCK and the negation of PCS.
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Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field Description Table 46-34. DSPI Baud Rate Scaler (continued) CTARn[BR] Baud Rate Scaler Value 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 46.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTAR_SLAVE) When the DSPI is configured as an SPI bus slave, the CTAR0 register is used.
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Chapter 46 SPI (DSPI) SPIx_CTARn_SLAVE field descriptions (continued) Field Description 0 1 Data is captured on the leading edge of SCK and changed on the following edge. Data is changed on the leading edge of SCK and captured on the following edge. 24–23 Reserved This read-only field is reserved and always has the value zero. 22–0 Reserved This read-only field is reserved and always has the value zero. 46.3.5 DSPI Status Register (SPIx_SR) SR contains status and flag bits.
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Memory Map/Register Definition SPIx_SR field descriptions (continued) Field Description 0 1 30 TXRXS TX and RX Status Reflects the run status of the DSPI. 0 1 29 Reserved 28 EOQF End of Queue Flag Indicates that the last entry in a queue has been transmitted when the DSPI is in master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer is reached. The EOQF bit remains set until cleared by writing a 1 to it.
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Chapter 46 SPI (DSPI) SPIx_SR field descriptions (continued) Field 19 RFOF Description Receive FIFO Overflow Flag Indicates an overflow condition in the RX FIFO. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit remains set until it is cleared by writing a 1 to it. 0 1 18 Reserved 17 RFDF This read-only field is reserved and always has the value zero. Receive FIFO Drain Flag Provides a method for the DSPI to request that entries be removed from the RX FIFO.
PAGE 1224
Memory Map/Register Definition 46.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER) RSER controls DMA and interrupt requests. Do not write to the RSER while the DSPI is in the Running state.
PAGE 1225
Chapter 46 SPI (DSPI) SPIx_RSER field descriptions (continued) Field Description 26 Reserved This read-only field is reserved and always has the value zero. 25 TFFF_RE Transmit FIFO Fill Request Enable Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit selects between generating an interrupt request or a DMA request. 0 1 24 TFFF_DIRS TFFF interrupts or DMA requests are disabled. TFFF interrupts or DMA requests are enabled.
PAGE 1226
Memory Map/Register Definition SPIx_RSER field descriptions (continued) Field Description 15–0 Reserved This read-only field is reserved and always has the value zero. 46.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR) PUSHR provides the means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the PUSHR transfer all 32 register bits to the TX FIFO. The register structure is different in master and slave modes.
PAGE 1227
Chapter 46 SPI (DSPI) SPIx_PUSHR field descriptions (continued) Field Description 27 EOQ End Of Queue Host software uses this bit to signal to the DSPI that the current SPI transfer is the last in a queue. At the end of the transfer, the EOQF bit in the SR is set. 0 1 26 CTCNT The SPI data is not the last data to transfer. The SPI data is the last data to transfer. Clear Transfer Counter. Clears the SPI_TCNT field in the TCR register.
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Memory Map/Register Definition SPIx_PUSHR_SLAVE field descriptions Field Description 31–0 TXDATA Transmit Data Holds SPI data to be transferred according to the associated SPI command. 46.3.9 DSPI POP RX FIFO Register (SPIx_POPR) POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to this register will generate a Transfer Error.
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Chapter 46 SPI (DSPI) 46.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn) TXFRn provide visibility into the TX FIFO for debugging purposes. Each register is an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the TXFRx registers does not alter the state of the TX FIFO.
PAGE 1230
Functional Description 46.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn) RXFRn provide visibility into the RX FIFO for debugging purposes. Each register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the RXFRx registers does not alter the state of the RX FIFO.
PAGE 1231
Chapter 46 SPI (DSPI) The CTARn registers hold clock and transfer attributes. The SPI configuration allows to select which CTAR to use on a frame by frame basis by setting a field in the SPI command. See DSPI Clock and Transfer Attributes Registers for information on the fields of the CTAR registers. Typical master to slave connections are shown in the following figure. When a data transfer operation is performed, data is serially shifted a predetermined number of bit positions.
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Functional Description The DSPI is started (DSPI transitions to RUNNING) when all of the following conditions are true: • SR[EOQF] bit is clear • MCU is not in the debug mode or the MCR[FRZ] bit is clear • MCR[HALT] bit is clear The DSPI stops (transitions from RUNNING to STOPPED) after the current frame when any one of the following conditions exist: • SR[EOQF] bit is set • MCU in the debug mode and the MCR[FRZ] bit is set • MCR[HALT] bit is set State transitions from RUNNING to STOPPED occur on the next
PAGE 1233
Chapter 46 SPI (DSPI) 46.4.2.1 Master Mode In SPI master mode the DSPI initiates the serial transfers by controlling the Serial Communications Clock (SCK) and the Peripheral Chip Select (PCS) signals. The SPI command field in the executing TX FIFO entry determines which CTAR registers will be used to set the transfer attributes and which PCS signals to assert. The command field also contains various bits that help with queue management and transfer protocol.
PAGE 1234
Functional Description 46.4.2.4 Transmit First In First Out (TX FIFO) Buffering Mechanism The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds 4 words, each consisting of a command field and a data field. The number of entries in the TX FIFO is device-specific. SPI commands and data are added to the TX FIFO by writing to the DSPI PUSH TX FIFO Register (PUSHR). TX FIFO entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
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Chapter 46 SPI (DSPI) If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TX FIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. See Transmit FIFO Underflow Interrupt Request for details. 46.4.2.5 Receive First In First Out (RX FIFO) Buffering Mechanism The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds 4 received SPI data frames. The number of entries in the RX FIFO is device-specific.
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Functional Description 46.4.2.5.2 Draining the RX FIFO Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the DSPI POP RX FIFO Register (POPR). A read of the POPR decrements the RX FIFO Counter by one. Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO Counter remains unchanged. The data, read from the empty RX FIFO, is undetermined. When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the SR is set.
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Chapter 46 SPI (DSPI) 46.4.3.2 PCS to SCK Delay (tCSC) The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See Figure 46-72 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the CTARx registers select the PCS to SCK delay by the formula in the CSSCK field description. The following table shows an example of how to compute the PCS to SCK delay. Table 46-81.
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Functional Description 46.4.3.4 Delay after Transfer (tDT) The Delay after Transfer is the minimum time between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame. See Figure 46-72 for an illustration of the Delay after Transfer. The PDT and DT fields in the CTARx registers select the Delay after Transfer by the formula in the DT field description. The following table shows an example of how to compute the Delay after Transfer. Table 46-83.
PAGE 1239
Chapter 46 SPI (DSPI) At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the CTAR based on the following formula: The following table shows an example of how to compute the tpcssck delay. Table 46-84. Peripheral Chip Select Strobe Assert Computation Example fsys PCSSCK Prescaler Delay before Transfer 100 MHz 0b11 7 70.0 ns The following table shows an example of how to compute the tpasc delay. Table 46-85.
PAGE 1240
Functional Description The DSPI supports four different transfer formats: • Classic SPI with CPHA=0 • Classic SPI with CPHA=1 • Modified Transfer format with CPHA = 0 • Modified Transfer format with CPHA = 1 A modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle to give the peripheral more setup time.
PAGE 1241
Chapter 46 SPI (DSPI) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK (CPOL = 0) SCK (CPOL = 1) Master and Slave Sample Master SOUT/ Slave SIN Master SIN/ Slave SOUT PCSx/SS tASC tDT t CSC tCSC Bit 6 Bit 5 Bit 4 MSB first (LSBFE = 0): MSB Bit 1 Bit 2 Bit 3 MSB first (LSBFE = 1): LSB tCSC = PCS to SCK delay tASC = After SCK delay tDT = Delay after Transfer (Minimum CS idle time) Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 46-72.
PAGE 1242
Functional Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK (CPOL = 0) SCK (CPOL = 1) Master and Slave Sample Master SOUT/ Slave SIN Master SIN/ Slave SOUT PCSx/SS tASC tDT tCSC Bit 4 Bit 5 Bit 3 MSB first (LSBFE = 0): MSB Bit 6 Bit 1 Bit 2 LSB first (LSBFE = 1): LSB Bit 4 Bit 3 P tCSC = CS to SCK delay tASC = After SCK delay tDT = Delay after Transfer (minimum CS negation time) Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 46-73.
PAGE 1243
Chapter 46 SPI (DSPI) When the CONT bit = 0, the DSPI drives the asserted Chip Select signals to their idle states in between frames. The idle states of the Chip Select signals are selected by the PCSISn bits in the MCR. The following timing diagram is for two four-bit transfers with CPHA = 1 and CONT = 0. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCSx tCSC t ASC t DT t CSC tCSC = PCS to SCK dela t ASC = After SCK delay t DT = Delay after Transfer (minimum CS negation time) Figure 46-74.
PAGE 1244
Functional Description • All transmit commands must have the same PCSn bits programming. • The CTARs, selected by transmit commands, must be programmed with the same transfer attributes. Only FMSZ field can be programmed differently in these CTARs.
PAGE 1245
Chapter 46 SPI (DSPI) • When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each SPI frame transfer, the CTAR specified by the CTAS for the frame is used. • In all configurations, the currently selected CTAR remains in use until the start of a frame with a different CTAR specified, or the Continuous SCK mode is terminated. It is recommended to keep the baud rate the same while using the Continuous SCK.
PAGE 1246
Functional Description • Continuous SCK with CONT bit set and entering STOPPED state (refer to Start and Stop of DSPI Transfers). • Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode. The following figure shows timing diagram for Continuous SCK format with Continuous Selection enabled. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCS transfer 1 transfer 2 Figure 46-77. Continuous SCK Timing Diagram (CONT=1) 46.4.
PAGE 1247
Chapter 46 SPI (DSPI) 46.4.7 Interrupts/DMA Requests The DSPI has several conditions that can only generate interrupt requests and two conditions that can generate interrupt or DMA requests. The following table lists these conditions. Table 46-86.
PAGE 1248
Functional Description 46.4.7.2 Transmit FIFO Fill Interrupt or DMA Request The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is generated when the number of entries in the TX FIFO is less than the maximum number of possible entries, and the TFFF_RE bit in the RSER is set. The TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is generated. NOTE TFFF flag clears automatically when DMA is used to fill TXFIFO.
PAGE 1249
Chapter 46 SPI (DSPI) 46.4.7.6 Receive FIFO Overflow Interrupt Request The Receive FIFO Overflow Request indicates that an overflow condition in the RX FIFO has occurred. A Receive FIFO Overflow request is generated when RX FIFO and shift register are full and a transfer is initiated. The RFOF_RE bit in the RSER must be set for the interrupt request to be generated.
PAGE 1250
Initialization/Application Information When the MDIS bit is set or the DOZE mode signal is asserted while the DOZE bit is set, the DSPI negates Clock Enable signal at the next frame boundary. If implemented, the Clock Enable signal can stop the clock to the non-memory mapped logic. When Clock Enable is negated, the DSPI is in a dormant state, but the memory mapped registers are still accessible. Certain read or write operations have a different effect when the DSPI is in the module disable mode.
PAGE 1251
Chapter 46 SPI (DSPI) 7. Modify DMA descriptor of TX and RX channels for new queues 8. Flush TX FIFO by writing a '1' to the CLR_TXF bit in the MCR. Flush RX FIFO by writing a '1' to the CLR_RXF bit in the MCR. 9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new queue or via CPU writing directly to SPI_TCNT field in the TCR. 10.
PAGE 1252
Initialization/Application Information Table 46-87. Baud Rate Values (bps) Baud Rate Scaler Values Baud Rate Divider Prescaler Values 2 3 5 7 2 25.0M 16.7M 10.0M 7.14M 4 12.5M 8.33M 5.00M 3.57M 6 8.33M 5.56M 3.33M 2.38M 8 6.25M 4.17M 2.50M 1.79M 16 3.12M 2.08M 1.25M 893k 32 1.56M 1.04M 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.
PAGE 1253
Chapter 46 SPI (DSPI) Table 46-88. Delay Values Delay Scaler Values Delay Prescaler Values 1 3 5 7 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 μs 32 320.0 ns 960.0 ns 1.6 μs 2.2 μs 64 640.0 ns 1.9 μs 3.2 μs 4.5 μs 128 1.3 μs 3.8 μs 6.4 μs 9.0 μs 256 2.6 μs 7.7 μs 12.8 μs 17.9 μs 512 5.1 μs 15.4 μs 25.6 μs 35.8 μs 1024 10.2 μs 30.7 μs 51.2 μs 71.
PAGE 1254
Initialization/Application Information Push TX FIFO Register TX FIFO Base Transmit Next Data Pointer Entry A (first in) Entry B Entry C Entry D (last in) - Shift Register +1 TX FIFO Counter SOUT -1 Figure 46-78. TX FIFO Pointers and Counter 46.5.5.
PAGE 1255
Chapter 46 SPI (DSPI) The memory address of the last-in entry in the RX FIFO is computed by the following equation: RX FIFO Base - Base address of RX FIFO RXCTR - RX FIFO counter POPNXTPTR - Pop Next Pointer RX FIFO Depth - Receive FIFO depth, implementation specific K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
PAGE 1256
Initialization/Application Information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1256 Freescale Semiconductor, Inc.
PAGE 1257
Chapter 47 Inter-Integrated Circuit (I2C) 47.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The inter-integrated circuit (I2C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
PAGE 1258
Introduction • • • • • • 10-bit address extension Support for System Management Bus (SMBus) Specification, version 2 Programmable glitch input filter Low power mode wakeup on slave address match Range slave address support DMA support 47.1.2 Modes of Operation The I2C module's operation in various low power modes is as follows: • Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module.
PAGE 1259
Chapter 47 Inter-Integrated Circuit (I2C) Address Module Enable Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync START STOP Arbitration Control Clock Control In/Out Data Shift Register Address Compare SDA SCL Figure 47-1. I2C Functional Block Diagram 47.2 I2C Signal Descriptions The signal properties of I2C are shown in the following table. Table 47-1.
PAGE 1260
Memory Map and Register Descriptions I2C memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_6000 I2C Address Register 1 (I2C0_A1) 8 R/W 00h 47.3.1/ 1261 4006_6001 I2C Frequency Divider register (I2C0_F) 8 R/W 00h 47.3.2/ 1261 4006_6002 I2C Control Register 1 (I2C0_C1) 8 R/W 00h 47.3.3/ 1262 4006_6003 I2C Status Register (I2C0_S) 8 R/W 80h 47.3.4/ 1264 4006_6004 I2C Data I/O register (I2C0_D) 8 R/W 00h 47.3.
PAGE 1261
Chapter 47 Inter-Integrated Circuit (I2C) I2C memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_7008 I2C SMBus Control and Status register (I2C1_SMB) 8 R/W 00h 47.3.9/ 1269 4006_7009 I2C Address Register 2 (I2C1_A2) 8 R/W C2h 47.3.10/ 1270 4006_700A I2C SCL Low Timeout Register High (I2C1_SLTH) 8 R/W 00h 47.3.11/ 1271 4006_700B I2C SCL Low Timeout Register Low (I2C1_SLTL) 8 R/W 00h 47.3.12/ 1271 1 0 47.3.
PAGE 1262
Memory Map and Register Descriptions I2Cx_F field descriptions Field 7–6 MULT Description The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the I2C baud rate. 00 01 10 11 5–0 ICR mul = 1 mul = 2 mul = 4 Reserved Clock rate Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time.
PAGE 1263
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description 0 1 6 IICIE I2C interrupt enable Enables I2C interrupt requests. 0 1 5 MST When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation changes from master to slave. Slave mode Master mode Transmit mode select Selects the direction of master and slave transfers.
PAGE 1264
Memory Map and Register Descriptions I2Cx_C1 field descriptions (continued) Field Description 0 1 All DMA signalling disabled. DMA transfer is enabled and the following conditions trigger the DMA request: • While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) • While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set.
PAGE 1265
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description 0 1 5 BUSY Bus busy Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. 0 1 4 ARBL Bus is idle Bus is busy Arbitration lost This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing a one to it.
PAGE 1266
Memory Map and Register Descriptions I2Cx_S field descriptions (continued) Field Description 0 1 Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected 47.3.
PAGE 1267
Chapter 47 Inter-Integrated Circuit (I2C) 47.3.6 I2C Control Register 2 (I2Cx_C2) Addresses: I2C0_C2 is 4006_6000h base + 5h offset = 4006_6005h I2C1_C2 is 4006_7000h base + 5h offset = 4006_7005h Bit Read Write Reset 7 6 5 4 3 GCAEN ADEXT HDRS SBRC RMEN 0 0 0 0 0 2 1 0 AD[10:8] 0 0 0 I2Cx_C2 field descriptions Field 7 GCAEN Description General call address enable Enables general call address. 0 1 6 ADEXT Address extension Controls the number of bits used for the slave address.
PAGE 1268
Memory Map and Register Descriptions 47.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT) Addresses: I2C0_FLT is 4006_6000h base + 6h offset = 4006_6006h I2C1_FLT is 4006_7000h base + 6h offset = 4006_7006h Bit 7 Read 0 6 5 4 3 0 0 0 1 0 0 0 FLT Write Reset 2 0 0 0 0 I2Cx_FLT field descriptions Field Description 7 Reserved This read-only field is reserved and always has the value zero. 6–5 Reserved This read-only field is reserved and always has the value zero.
PAGE 1269
Chapter 47 Inter-Integrated Circuit (I2C) 47.3.9 I2C SMBus Control and Status register (I2Cx_SMB) NOTE When the SCL and SDA signals are held high for a length of time greater than the high timeout period, the SHTF1 flag sets. Before reaching this threshold, while the system is detecting how long these signals are being held high, a master assumes that the bus is free. However, the SHTF1 bit rises in the bus transmission process with the idle bus state.
PAGE 1270
Memory Map and Register Descriptions I2Cx_SMB field descriptions (continued) Field Description 0 1 4 TCKSEL Timeout counter clock select Selects the clock source of the timeout counter.
PAGE 1271
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_A2 field descriptions Field 7–1 SAD Description SMBus address Contains the slave address used by the SMBus. This field is used on the device default address or other related addresses. 0 Reserved This read-only field is reserved and always has the value zero. 47.3.
PAGE 1272
Functional Description 47.4 Functional Description This section provides a comprehensive functional description of the I2C module. 47.4.1 I2C Protocol The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors depends on the system.
PAGE 1273
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.1.1 START Signal The bus is free when no master device is engaging the bus (both SCL and SDA are high). When the bus is free, a master may initiate communication by sending a START signal. A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer might contain several bytes of data) and brings all slaves out of their idle states. 47.4.1.
PAGE 1274
Functional Description If the slave receiver does not acknowledge the master in the ninth bit, the slave must leave SDA high. The master interprets the failed acknowledgement as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets it as an end to data transfer and releases the SDA line.
PAGE 1275
Chapter 47 Inter-Integrated Circuit (I2C) stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of arbitration. 47.4.1.7 Clock Synchronization Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects all devices connected on the bus.
PAGE 1276
Functional Description 47.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master drives SCL low, a slave can drive SCL low for the required period and then release it. If the slave's SCL low period is greater than the master's SCL low period, the resulting SCL bus signal's low period is stretched. 47.4.1.10 I2C Divider and Hold Values Table 47-41.
PAGE 1277
Chapter 47 Inter-Integrated Circuit (I2C) Table 47-41.
PAGE 1278
Functional Description After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the Data register are ignored and not treated as valid data. 47.4.2.2 Master-Receiver Addresses a Slave-Transmitter The transfer direction is changed after the second R/W bit.
PAGE 1279
Chapter 47 Inter-Integrated Circuit (I2C) address matching process.If the Range Address register is programmed to a nonzero value, the range address itself participates in the address matching process. If the RMEN bit is set, any address within the range of values of the Address Register 1 and the Range Address register participates in the address matching process. The Range Address register must be programmed to a value greater than the value of the Address Register 1.
PAGE 1280
Functional Description the I2C module is an active master, if it detects that SMBCLK low has exceeded the value of TTIMEOUT,MIN, it must generate a stop condition within or after the current data byte in the transfer process. When the I2C module is a slave, if it detects the TTIMEOUT,MIN condition, it resets its communication and is then able to receive a new START condition. 47.4.4.1.
PAGE 1281
Chapter 47 Inter-Integrated Circuit (I2C) Stop T LOW:SEXT Start T LOW:MEXT ClkAck T LOW:MEXT ClkAck T LOW:MEXT SCL SDA Figure 47-40. Timeout measurement intervals A master is allowed to abort the transaction in progress to any slave that violates the TLOW:SEXT or TTIMEOUT,MIN specifications. To abort the transaction, the master issues a STOP condition at the conclusion of the byte transfer in progress.
PAGE 1282
Functional Description have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This requirement is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
PAGE 1283
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.6.1 Byte Transfer Interrupt The transfer complete flag (TCF) bit is set at the falling edge of the ninth clock to indicate the completion of a byte and acknowledgement transfer. When FACK is enabled, TCF is then set at the falling edge of 8th clock to indicate the completion of byte. 47.4.6.
PAGE 1284
Functional Description The ARBL bit must be cleared (by software) by writing 1 to it. 47.4.6.5 Timeout Interrupt in SMBus When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and SHTF2) upon detection of any of the mentioned timeout conditions, with one exception. The SCL high and SDA high TIMEOUT mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus.
PAGE 1285
Chapter 47 Inter-Integrated Circuit (I2C) NOTE After the system recovers and is in run mode, restart the I2C module if necessary. The SCL line is not held low until the I2C module resets after address matching. The main purpose of this feature is to wake the MCU from stop mode. Data sent on the bus that is the same as a target device address might also wake the target MCU. 47.4.9 DMA Support If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an interrupt request.
PAGE 1286
Initialization/Application Information Module Initialization (Master) 1. Write: Frequency Divider register to set the I2C baud rate (example provided in this chapter) 2. Write: Control Register 1 to enable the I2C module and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown in the following figure 5. Write: Control Register 1 to enable TX 6. Write: Control Register 1 to enable MST (master mode) 7.
PAGE 1287
Chapter 47 Inter-Integrated Circuit (I2C) Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Arbitration lost? N Clear ARBL N N Last byte to be read? RXAK=0? N End of address cycle (master Rx)? Y Y (read) 2nd to last byte to be read? Write next byte to Data reg Set TXACK Address transfer see note 1 N Data transfer see note 2 Tx/Rx? Tx Y Generate stop signal (MST=0) IIAAS=1? Rx SRW=1? N (write) N N Y IIAAS=1? Y N Y Y Y Set TX mode ACK from receiver? N W
PAGE 1288
Initialization/Application Information Y N SLTF or SHTF2=1? N FACK=1? See typical I2C interrupt routine flow chart Y Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Last byte to be read? Y N RXAK=0? 2nd to last byte to be read? N N Y N Clear IICIF Y (read) Delay (note 2) Read data and Soft CRC Set TXAK to proper value Delay (note 2) Set TXACK=1 Clear FACK=0 Write next byte to Data reg Switch to Rx mode Generate stop signal (MST=0) Y IAAS=1? Y Delay (note 2
PAGE 1289
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The UART allows asynchronous serial communication with peripheral devices and CPUs. 48.1.1 Features The UART includes these distinctive features: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
PAGE 1290
Introduction • 11-bit break character detection option • Independent FIFO structure for transmit and receive • Two receiver wakeup methods: • Idle line wakeup • Address mark wakeup • Address match feature in receiver to reduce address mark wakeup ISR overhead • Ability to select MSB or LSB to be first bit on wire • Hardware flow control support for request to send (RTS) and clear to send (CTS) signals • Support for ISO 7816 protocol for interfacing with SIM cards and smart cards • Support of T=0 and T=1 pr
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) • Receiver data buffer overrun • Receiver data buffer underflow • Transmit data buffer overflow • Noise error • Framing error • Parity error • Active edge on receive pin • LIN break detect • Receiver framing error detection • Hardware parity generation and checking • 1/16 bit-time noise detection • DMA interface 48.1.2 Modes of operation The UART functions the same in all the normal modes. It has two low power modes: Wait and Stop modes. 48.1.
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UART signal descriptions The C1[UARTSWAI] bit does not initiate any power down or power up procedures for the smartcard (ISO-7816) interface. Setting C1[UARTSWAI] does not affect the state of the C2[RE], or C2[TE]. If C1[UARTSWAI] is set, any transmission or reception in progress stops at Wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of Wait mode.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Table 48-2. UART—Detailed signal descriptions Signal I/O Description CTS I Clear to send. Indicates whether the UART can start to transmit data when flow control is enabled. State meaning Asserted—Data transmission can start. Negated—Data transmission can not start. Timing Assertion—When transmitting device's RTS asserts. Negation—When transmitting device's RTS deasserts. RTS O Request to send.
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Memory map and registers UART memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A000 UART Baud Rate Registers:High (UART0_BDH) 8 R/W 00h 48.3.1/ 1300 4006_A001 UART Baud Rate Registers: Low (UART0_BDL) 8 R/W 04h 48.3.2/ 1301 4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h 48.3.3/ 1302 4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h 48.3.4/ 1303 4006_A004 UART Status Register 1 (UART0_S1) 8 R C0h 48.3.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A015 UART FIFO Receive Watermark (UART0_RWFIFO) 8 R/W 01h 48.3.21/ 1325 4006_A016 UART FIFO Receive Count (UART0_RCFIFO) 8 R 00h 48.3.22/ 1326 4006_A018 UART 7816 Control Register (UART0_C7816) 8 R/W 00h 48.3.23/ 1326 4006_A019 UART 7816 Interrupt Enable Register (UART0_IE7816) 8 R/W 00h 48.3.
PAGE 1296
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B009 UART Match Address Registers 2 (UART1_MA2) 8 R/W 00h 48.3.10/ 1314 4006_B00A UART Control Register 4 (UART1_C4) 8 R/W 00h 48.3.11/ 1314 4006_B00B UART Control Register 5 (UART1_C5) 8 R/W 00h 48.3.12/ 1315 4006_B00C UART Extended Data Register (UART1_ED) 8 R 00h 48.3.
PAGE 1297
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B01E UART 7816 Error Threshold Register (UART1_ET7816) 8 R/W 00h 48.3.30/ 1333 4006_B01F UART 7816 Transmit Length Register (UART1_TL7816) 8 R/W 00h 48.3.31/ 1334 4006_C000 UART Baud Rate Registers:High (UART2_BDH) 8 R/W 00h 48.3.
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Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_C013 UART FIFO Transmit Watermark (UART2_TWFIFO) 8 R/W 00h 48.3.19/ 1324 4006_C014 UART FIFO Transmit Count (UART2_TCFIFO) 8 R 00h 48.3.20/ 1324 4006_C015 UART FIFO Receive Watermark (UART2_RWFIFO) 8 R/W 01h 48.3.21/ 1325 4006_C016 UART FIFO Receive Count (UART2_RCFIFO) 8 R 00h 48.3.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_D007 UART Data Register (UART3_D) 8 R/W 00h 48.3.8/ 1312 4006_D008 UART Match Address Registers 1 (UART3_MA1) 8 R/W 00h 48.3.9/ 1313 4006_D009 UART Match Address Registers 2 (UART3_MA2) 8 R/W 00h 48.3.10/ 1314 4006_D00A UART Control Register 4 (UART3_C4) 8 R/W 00h 48.3.
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Memory map and registers UART memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_D01C UART 7816 Wait N Register (UART3_WN7816) 8 R/W 00h 48.3.28/ 1332 4006_D01D UART 7816 Wait FD Register (UART3_WF7816) 8 R/W 01h 48.3.29/ 1333 4006_D01E UART 7816 Error Threshold Register (UART3_ET7816) 8 R/W 00h 48.3.30/ 1333 4006_D01F UART 7816 Transmit Length Register (UART3_TL7816) 8 R/W 00h 48.3.31/ 1334 48.3.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_BDH field descriptions (continued) Field Description 0 1 5 Reserved 4–0 SBR Hardware interrupts from RXEDGIF disabled (use polling). RXEDGIF interrupt request enabled. This read-only field is reserved and always has the value zero. UART Baud Rate Bits The baud rate for the UART is determined by these 13 bits. See Baud rate generation for details.
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Memory map and registers 48.3.3 UART Control Register 1 (UARTx_C1) This read/write register controls various optional features of the UART system.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C1 field descriptions (continued) Field 2 ILT Description Idle Line Type Select ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit can cause false recognition of an idle character.
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Memory map and registers UARTx_C2 field descriptions Field 7 TIE Description Transmitter Interrupt or DMA Transfer Enable. TIE enables the S1[TDRE] flag, to generate interrupt requests or DMA transfer requests, based on the state of C5[TDMAS]. NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be written outside of servicing of a DMA request.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C2 field descriptions (continued) Field Description NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently not idle. This can be determined by the S2[RAF] flag. If set to wake up an IDLE event and the channel is already idle, it is possible that the UART will discard data since data must be received (or a LIN break detect) after an IDLE is detected before IDLE is allowed to reasserted.
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Memory map and registers Addresses: UART0_S1 is 4006_A000h base + 4h offset = 4006_A004h UART1_S1 is 4006_B000h base + 4h offset = 4006_B004h UART2_S1 is 4006_C000h base + 4h offset = 4006_C004h UART3_S1 is 4006_D000h base + 4h offset = 4006_D004h Bit Read 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PF 1 1 0 0 0 0 0 0 Write Reset UARTx_S1 field descriptions Field 7 TDRE Description Transmit Data Register Empty Flag TDRE will set when the number of datawords in the transmit buffer
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S1 field descriptions (continued) Field 4 IDLE Description Idle Line Flag IDLE is set when 10 consecutive logic 1s (if C1[M] = 0), 11 consecutive logic 1s (if C1[M] = 1 and C4[M10] = 0), or 12 consecutive logic 1s (if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1) appear on the receiver input.
PAGE 1308
Memory map and registers UARTx_S1 field descriptions (continued) Field 0 PF Description Parity Error Flag PF is set when PE is set, S2[LBKDE] is disabled, and the parity of the received data does not match its parity bit. The PF is not set in the case of an overrun condition. When the PF bit is set it only indicates that a dataword was received with parity error since the last time it was cleared.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S2 field descriptions (continued) Field 6 RXEDGIF Description RxD Pin Active Edge Interrupt Flag RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a 1 to it. See RXEDGIF description for additional details. NOTE: The active edge is only detected when in two wire mode and on receive data coming from the RxD pin.
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Memory map and registers UARTx_S2 field descriptions (continued) Field Description LBKDE selects a longer break character detection length. While LBKDE is set, the S1[RDRF], S1[NF], S1[FE], and S1[PF] flags are prevented from setting. When LBKDE is set, see Overrun operation. The LBKDE bit must be cleared when C7816[ISO7816E] is set. 0 1 0 RAF Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C3 field descriptions (continued) Field Description T8 is the ninth data bit transmitted when the UART is configured for 9-bit data format (C1[M] = 1) or (C4[M10] = 1). NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same value is transmitted until T8 is rewritten.
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Memory map and registers UARTx_C3 field descriptions (continued) Field Description This bit enables the parity error flag (S1[PF]) to generate interrupt requests. 0 1 PF interrupt requests are disabled. PF interrupt requests are enabled. 48.3.8 UART Data Register (UARTx_D) This register is actually two separate registers. Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Addresses: UART0_D is 4006_A000h base + 7h offset = 4006_A007h UART1_D is 4006_B000h base + 7h offset = 4006_B007h UART2_D is 4006_C000h base + 7h offset = 4006_C007h UART3_D is 4006_D000h base + 7h offset = 4006_D007h Bit 7 6 5 4 Read 2 1 0 0 0 0 0 RT Write Reset 3 0 0 0 0 UARTx_D field descriptions Field 7–0 RT Description Reads return the contents of the read-only receive data register and writes go to the write-only trans
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Memory map and registers 48.3.10 UART Match Address Registers 2 (UARTx_MA2) These registers can be read and written at anytime. The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C4 field descriptions (continued) Field Description discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. 6 MAEN2 Match Address Mode Enable 2 Refer to Match address operation for more information. 0 1 5 M10 All data received is transferred to the data buffer if MAEN1 is cleared. All data received with the most significant bit cleared, is discarded.
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Memory map and registers UARTx_C5 field descriptions (continued) Field Description NOTE: If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D register must not be written outside of servicing of a DMA request. 0 1 6 Reserved 5 RDMAS If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Addresses: UART0_ED is 4006_A000h base + Ch offset = 4006_A00Ch UART1_ED is 4006_B000h base + Ch offset = 4006_B00Ch UART2_ED is 4006_C000h base + Ch offset = 4006_C00Ch UART3_ED is 4006_D000h base + Ch offset = 4006_D00Ch Bit Read 7 6 NOISY PARITYE 0 0 5 4 3 2 1 0 0 0 0 0 Write Reset 0 0 0 UARTx_ED field descriptions Field 7 NOISY Description The current received dataword contained in D and C3[R8] was received with noise.
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Memory map and registers UARTx_MODEM field descriptions Field Description 7–4 Reserved This read-only field is reserved and always has the value zero. 3 RXRTSE Receiver request-to-send enable Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun. NOTE: Do not set both RXRTSE and TXRTSE. 0 1 2 TXRTSPOL Transmitter request-to-send polarity Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.15 UART Infrared Register (UARTx_IR) The IR register controls options for setting the infrared configuration.
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Memory map and registers 48.3.16 UART FIFO Parameters (UARTx_PFIFO) This register provides the ability for the programmer to turn on and off FIFO functionality. It also provides the size of the FIFO that has been implemented. This register may be read at any time. This register should only be written when the C2[RE] and C2[TE] bits are cleared / not set and when the data buffer/FIFO is empty.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_PFIFO field descriptions (continued) Field Description 110 111 3 RXFE Transmit FIFO/Buffer Depth = 128 Datawords. Reserved. Receive FIFO Enable When this bit is set the built in FIFO structure for the receive buffer is enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. If this bit is not set then the receive buffer operates as a FIFO of depth one dataword regardless of the value in RXFIFOSIZE.
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Memory map and registers UARTx_CFIFO field descriptions Field 7 TXFLUSH Description Transmit FIFO/Buffer Flush Writing to this bit causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not affect data that is in the transmit shift register. 0 1 6 RXFLUSH Receive FIFO/Buffer Flush Writing to this bit causes all data that is stored in the receive FIFO/buffer to be flushed. This does not affect data that is in the receive shift register.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_SFIFO field descriptions Field 7 TXEMPT Description Transmit Buffer/FIFO Empty This status bit asserts when there is no data in the Transmit FIFO/buffer. This bit does not take into account data that is in the transmit shift register. 0 1 6 RXEMPT Receive Buffer/FIFO Empty This status bit asserts when there is no data in the receive FIFO/Buffer. This bit does not take into account data that is in the receive shift register.
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Memory map and registers 48.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO) This register provides the ability to set a programmable threshold for notification of needing additional transmit data. This register may be read at any time but should only be written when C2[TE] is not set. Changing the value of the watermark will not clear the S1[TDRE] flag.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_TCFIFO field descriptions Field 7–0 TXCOUNT Description Transmit Counter The value in this register indicates the number of datawords that are in the transmit buffer/FIFO. If a dataword is in the process of being transmitted (i.e. in the transmit shift register) it is not included in the count. This value may be used in conjunction with the PFIFO[TXFIFOSIZE] field to calculate how much room is left in the transmit buffer/FIFO. 48.3.
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Memory map and registers 48.3.22 UART FIFO Receive Count (UARTx_RCFIFO) This is a read only register that indicates how many datawords are currently in the receive buffer/FIFO. It may be read at anytime.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C7816 field descriptions Field 7–5 Reserved 4 ONACK Description This read-only field is reserved and always has the value zero. Generate NACK on Overflow When this bit is set, the receiver will automatically generate a NACK response if a receive buffer overrun occurs as indicated by the S1[OR] field.
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Memory map and registers 48.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816) The IE7816 register controls which flags result in an interrupt being issued. This register is specific to 7816 functionality, the corresponding flags that drive the interrupts will not assert when 7816E is not set/enabled. However, these flags may remain set if they asserted while 7816E was set and not subsequently cleared. This register maybe read or written at anytime.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_IE7816 field descriptions (continued) Field 0 RXTE Description Receive Threshold Exceeded Interrupt Enable 0 1 The assertion of the IS7816[RXT] bit will not result in the generation of an interrupt. The assertion of the IS7816[RXT] bit will result in the generation of an interrupt. 48.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816) The IS7816 register provides a mechanism to read and clear the interrupt flags.
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Memory map and registers UARTx_IS7816 field descriptions (continued) Field 5 BWT Description Block Wait Timer Interrupt This flag indicates that the block wait time, the time between the leading edge of first received character of a block and the leading edge of the last character the previously transmitted block. This flag only asserts when C7816[TTYPE] = 1.This interrupt is cleared by writing '1'.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816T0) The WP7816 register contains constants used in the generation of various wait timer counters. To save register space this register is used differently when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at anytime. This register must only be written when C7816[ISO_7816E] is not set.
PAGE 1332
Memory map and registers UARTx_WP7816T1 field descriptions Field Description 7–4 CWI Character Wait Time Integer (C7816[TTYPE] = 1) 3–0 BWI Block Wait Time Integer(C7816[TTYPE] = 1) This value is used to calculate the value used for the CWT counter. It represents a value between 0 and 15. This value is only used when C7816[TTYPE] = 1. See Wait time and guard time parameters. This value is used to calculate the value used for the BWT counter. It represent a value between 0 and 15.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.29 UART 7816 Wait FD Register (UARTx_WF7816) The WF7816 contains parameters that are used in the generation of various counters including GT, CGT, BGT, WT and BWT. This register may be read from at anytime. This register must only be written to when C7816[ISO_7816E] is not set.
PAGE 1334
Memory map and registers UARTx_ET7816 field descriptions (continued) Field Description The value written to this field indicates the maximum number of failed attempts (NACKs) a transmitted character can have before the host processor is notified. Meaning a value of 0 will always result in TXT asserting on the first NACK that is received. A value of 1 will result in TXT being asserted on the second NACK that is received. This field is only meaningful when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4 Functional description This section provides a complete functional description of the UART block. The UART allows full duplex, asynchronous, NRZ serial communication between the CPU and remote devices, including other CPUs. The UART transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the UART, writes the data to be transmitted, and processes received data. 48.4.
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Functional description 48.4.1.1 Transmitter character length The UART transmitter can accommodate either 8, 9, or 10-bit data characters. The state of the C1[M] and C1[PE] bits and the C4[M10] bit determine the length of data characters. When transmitting 9-bit data, bit C3[T8] is the ninth bit (bit 8). 48.4.1.2 Transmission bit order When the S2[MSBF] bit is set, the UART automatically transmits the MSB of the data word as the first bit after the start bit.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) When C7816[ISO_7816E] = 1 setting the C2[TE] bit does not result in a preamble being generated. The transmitter starts transmitting as soon as the corresponding guard time expires. When C7816[TTYPE] = 0 the value in GT is used, when C7816[TTYPE] = 1 the value BGT is used since it is assumed that the C2[TE] will remain asserted until the end of the block transfer.
PAGE 1338
Functional description Table 48-163. Transmit break character length (continued) S2[BRK13] C1[M] C4[M10] C1[PE] Bits transmitted 0 1 0 — 11 0 1 1 0 11 0 1 1 1 12 1 0 — — 13 1 1 — — 14 As long as C2[SBK] is set, transmitter logic continuously loads break characters into the transmit shift register. After software clears the C2[SBK] bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) is queued in the data buffer to be transmitted, the idle character will preempt that queued data. The queued data will then be transmitted after the idle character is complete. If the C2[TE] bit is cleared and the transmission is completed, the UART is not the master of the TXD pin. 48.4.1.6 Hardware flow control The transmitter supports hardware flow control by gating the transmission with the value of CTS.
PAGE 1340
Functional description C1 in transmission TXD data buffer write C1 1 C1 C2 C2 C3 Break C3 C4 Start Stop Break Break C4 C5 C5 CTS_B RTS_B 1. Cn = transmit characters Figure 48-157. Transmitter RTS and CTS timing diagram K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1340 Freescale Semiconductor, Inc.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.2 Receiver INTERNAL BUS BRFA4:0 RE RAF BAUDRATE GENERATOR STOP MODULE CLOCK DATA BUFFER VARIABLE 12-BIT RECEIVE SHIFT REGISTER START SBR12:0 RECEIVE CONTROL M M10 LBKDE MSBF RXINV SHIFT DIRECTION RxD LOOPS RSRC RECEIVER SOURCE CONTROL PE PT From Transmitter RxD PARITY LOGIC WAKEUP LOGIC IRQ / DMA LOGIC ACTIVE EDGE DETECT DMA Requests IRQ Requests To TxD 7816 LOGIC INFRARED LOGIC Figure 48-158.
PAGE 1342
Functional description the data word. All necessary bit ordering is handled automatically by the module hence the format of the data read from receive data buffer is completely independent of the S2[MSBF] setting. 48.4.2.3 Character reception During UART reception, the receive shift register shifts a frame in from the unsynchronized receiver input signal. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the UART receive buffer.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) • After every start bit. • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0). To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.
PAGE 1344
Functional description To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. The following table summarizes the results of the data bit samples. Table 48-165. Data bit recovery RT8, RT9, and RT10 samples Data bit determination Noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 Note The RT8, RT9, and RT10 samples do not affect start bit verification.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) In the following figure, the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. In this example C7816[ISO_7816E] = 0. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Functional description PERCEIVED START BIT LSB ACTUAL START BIT RT1 RT1 1 0 0 0 0 0 RT10 0 RT9 1 RT8 1 RT7 1 RT1 SAMPLES RT1 Rx pin input RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT CLOCK COUNT RT2 RT CLOCK RESET RT CLOCK Figure 48-162. Start bit search example 3 (C7816[ISO_7816E] = 0) The following figure shows the effect of noise early in the start bit time. In this example C7816[ISO_7816E] = 0.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) START BIT NO START BIT FOUND 0 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 1 0 1 0 0 0 0 0 0 0 0 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 LSB RT7 1 RT1 SAMPLES RT1 Rx pin input RT1 RT1 RT1 RT1 RT6 RT5 RT4 RT3 RT CLOCK COUNT RT2 RT CLOCK RESET RT CLOCK Figure 48-164.
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Functional description 48.4.2.6 Receiving break characters The UART recognizes a break character when a start bit is followed by eight, nine, or ten logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on UART registers: • Sets the framing error flag, S1[FE]. • Writes an all "0" dataword to the data buffer, which may cause S1[RDRF] to set depending on the watermark and number of values in the data buffer.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.2.7 Hardware flow control To support hardware flow control, the receiver can be programmed to automatically deassert and assert RTS. • RTS will remain asserted until the transfer is completed, even if the transmitter is disabled mid way through a data transfer, see Transceiver driver enable using RTS for more details.
PAGE 1350
Functional description 48.4.2.8.1 Start bit detection When S2[RXINV] is cleared, the first rising edge of the received character corresponds to the start bit. The infrared decoder resets its counter. At this time, the receiver also begins its start bit detection process. Once the start bit is detected, the receiver synchronizes its bit times to this start bit time.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 48.4.2.9.1 Slow data tolerance The following figure shows how much a slow received frame can be misaligned without causing a noise error or a framing error.
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Functional description 48.4.2.9.2 Fast data tolerance The following figure shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. IDLE OR NEXT FRAME STOP RT16 RT15 RT14 RT13 RT12 DATA SAMPLES RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK Figure 48-168.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.2.10.1 Idle input line wakeup (C1[WAKE] = 0) In this wakeup method, an idle condition on the unsynchronized receiver input signal clears the C2[RWU] bit and wakes the UART. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow.
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Functional description 48.4.2.10.3 Match address operation Match address operation is enabled when the C4[MAEN1] or C4[MAEN2] bit is set. In this function, a frame received by the RX pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated MA1 or MA2 register. The frame is only transferred to the receive buffer, and S1[RDRF] is set, if the comparison matches.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) The Table 48-168 lists the available baud divisor fine adjust values. UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD)) The following table lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz, with and without fractional fine adjustment. Table 48-168. Baud rates (example: module clock = 10.
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Functional description Table 48-169. Baud rate fine adjust (continued) BRFA Baud Rate Fractional Divisor (BRFD) 01101 13/32 = 0.40625 01110 14/32 = 0.4375 01111 15/32 = 0.46875 10000 16/32 = 0.5 10001 17/32 = 0.53125 10010 18/32 = 0.5625 10011 19/32 = 0.59375 10100 20/32 = 0.625 10101 21/32 = 0.65625 10110 22/32 = 0.6875 10111 23/32 = 0.71875 11000 24/32 = 0.75 11001 25/32 = 0.78125 11010 26/32 = 0.8125 11011 27/32 = 0.84375 11100 28/32 = 0.875 11101 29/32 = 0.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Table 48-170. Configuration of 8-bit data format UART_C1[PE] Start Data Address Parity Stop bit bits bits bits bit 1 8 0 0 1 0 1 1 1 0 0 1 7 11 1 1 7 0 1. The address bit identifies the frame as an address character. See Receiver wakeup. 48.4.4.2 Nine-bit configuration When UARTx_C1[M] is set and UARTx_C4[M10] is cleared the UART is configured for 9-bit data characters.
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Functional description 1. The address bit identifies the frame as an address character. 2. The address bit identifies the frame as an address character. Note Unless in 9-bit mode with M10 set, do not use address mark wakeup with parity enabled. 48.4.4.3 Timing examples Timing examples of these configurations in the NRZ mark/space data format are illustrated in the following figures.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) ADDRESS MARK START BIT 8 BIT 7 BIT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 START BIT 0 STOP BIT BIT Figure 48-174. Nine bits of data with MSB first 48.4.4.3.4 Nine-bit format with parity enabled START BIT 0 BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 START BIT 7 PARITY STOP BIT BIT Figure 48-175.
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Functional description Enable single-wire operation by setting the C1[LOOPS] bit and the receiver source bit, C1[RSRC]. Setting the C1[LOOPS] bit disables the path from the unsynchronized receiver input signal to the receiver. Setting the C1[RSRC] bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (C2[TE] = 1 and C2[RE] = 1). When C7816[ISO_7816EN] is set, it is not a requirement that both C2[TE] and C2[RE] are set. 48.4.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Additionally the module is able to provide automated NACK responses and has programing automated retransmission of failed packets. An assortment of programmable timeouts and guard band times are also supported. The term elemental time unit (ETU) is frequently used in the context of ISO-7816. This concept is used to relate the frequency that the system (UART) is running at and the frequency that data is being transmitted and received.
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Functional description When the C7816[INIT] bit is set, the receiver will search all received data for the first valid initial character. All data received which is not a valid initial character will be ignored and all flags resulting from the invalid data will be blocked from asserting. If the C7816[ANACK] bit is set, a NACK will be returned for invalid received initial characters and a RXT interrupt will be generated as programmed. 48.4.7.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) ISO 7816 FORMAT (T=1) START BIT 0 BIT PARITY BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT START STOP BIT BIT Figure 48-182. ISO 7816 T=1 data format The smallest data unit that is transferred is a block. A block is made up of several data characters and may vary in size depending on the block type. The UART does not provide a mechanism to decode the block type. As part of the block, an LRC or CRC is included.
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Functional description (transmission or reception). Block guard time (BGT) is the minimum allowable time between the leading edges of two consecutive characters in opposite directions (transmission then reception or reception then transmission). The GT and WT counters reset whenever C7816[TTYPE] = 1 or C7816[ISO_7816E] = 0 or a new dataword start bit has been received or transmitted as specified by the counter descriptions.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.7.6 UART restrictions in ISO-7816 operation Due to the flexibility of the UART module, there are several features and interrupts that are not supported while running in ISO-7816 mode. These restrictions are documented within the register bit definitions. 48.4.
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Reset 48.4.8.2 Infrared receive decoder The infrared receive block converts data from the RXD signal to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when S2[RXINV] is cleared, while a narrow low pulse is expected for a zero bit when S2[RXINV] is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification. 48.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Table 48-174. UART interrupt sources (continued) Interrupt Source Flag Local enable DMA select Receiver WT WTWE - Receiver CWT CWTE - Receiver BWT BWTE - Receiver INITD INITDE - Receiver TXT TXTE - Receiver RXT RXTE - Receiver GTV GTVE - 48.6.1 RXEDGIF description The S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Hence, the active edge can only be detected when in two wire mode.
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DMA operation 48.6.1.3 Exit from low-power modes The receive input active edge detect circuit is still active on low power modes (wait and stop). An active edge on the receive input brings the CPU out of low power mode if the interrupt is not masked (S2[RXEDGIF]=1). 48.7 DMA operation In the transmitter, flags S1[TDRE] can be configured to assert a DMA transfer request. In the receiver, flag S1[RDRF], can be configured to assert a DMA transfer request.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) operate as a depth of one. This is the default/reset behavior of the module and can be adjusted using the PFIFO[RXFE] and PFIFO[TXFE] bits. Individual watermark levels are also provided for transmit and receive. There are multiple ways to ensure that a data block (set of characters) has completed transmission. These methods include: 1. Set TXFIFO[TXWATER] to 0. The TDRE flag will assert when there is no further data in the transmit buffer.
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Application information 6. Write to set up interrupt enable bits desired (C3[ORIE], C3[NEIE], C3[PEIE], and C3[FEIE]) 7. Write to set C4[MAEN1] = 0 and C4[MAEN2] = 0. 8. Write to C5 register and configure DMA control register bits as desired for application. 9. Write to set C7816[INIT] = 1,C7816[ TTYPE] = 0, 7C7816[ISO_7816E] = 1. Program C7816[ONACK] and C7816[ANACK] as desired. 10. Write to IE7816 register to set interrupt enable parameters as desired. 11. Write to ET7816 register and set as desired. 12.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.8.2.2 Transmission procedure for (C7816[TTYPE] = 1) When the protocol selected is C7816[TTYPE] = 1, data is transferred in blocks. Prior to starting a transmission software should write the size (number of bytes) for the Information Field portion of the block in to the TLEN register. If a CRC is being transmitted for the block the value in TLEN should be one more than the size of the information field.
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Application information b. If the TDRE flag is set, or there is space in the transmit buffer, write the data to be transmitted to (C3[T8]/D). A new transmission will not result until data exists in the transmit buffer. 3. Repeat step 2 for each subsequent transmission.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) In most applications since the total amount of lost data is known, the application will desire to return the system to a known state. Prior to the S1[OR] flag being cleared all received data will be dropped. To do this the software would: 1. Remove data from the receive data buffer.
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Application information committed to prior to the dataword being fully received. While the NACK is being received it is possible that the application code will read the data buffer such that sufficient room will be made to store the dataword that is being NACKed. Even if room has been made in the data buffer once the transmission of a NACK is completed, the received data will always be discarded as a result of an overflow and the ET7816[RXTHRESHOLD] value will be incremented by one.
PAGE 1375
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.8.7.2 Transceiver driver enable using RTS RS-485 is a multiple drop communication protocol in which the UART transceiver's driver is 3-stated unless that UART is driving. The RTS signal can be used by the transmitter to enable the driver of a transceiver. The polarity of RTS can be matched to the polarity of the transceiver's driver enable signal. Refer to the following figure.
PAGE 1376
Application information 4. After the WT interrupt has been cleared, the smartcard remains unresponsive. At cycle 9701 the WT interrupt will reasserted. If the intent of clearing the interrupt is such that it does not reassert, the interrupt service routine must remove or clear the condition that originally caused the interrupt to assert prior to clearing the interrupt.
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Chapter 49 Secured digital host controller (SDHC) 49.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The chapter is intended for a module driver software developer. It describes module-level operation and programming. 49.2 Overview 49.2.
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Overview card, which is also known as SDIO card, provides high-speed data I/O with low power consumption for mobile electronic devices. For the sake of simplicity, the figure does not show cards with reduced size or mini cards. Host Controller DMA Interface Crossbar switch Peripheral bus Card Slot Transceiver MMC/SD/SDIO MMC card SD card SDIO card Power Supply Figure 49-1. System connection of the SDHC CE-ATA is a hard drive interface that is optimized for embedded applications storage.
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Chapter 49 Secured digital host controller (SDHC) 49.2.
PAGE 1380
Overview • Designed to work with CE-ATA, SD memory, miniSD memory, SDIO, miniSDIO, SD Combo, MMC, MMC plus, and MMC RS cards • Card bus clock frequency up to 52 MHz • Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes, 1-bit / 4-bit / 8-bit CE-ATA devices • Up to 200 Mbps of data transfer for SD/SDIO cards using 4 parallel data lines • Up to 416 Mbps of data transfer for MMC cards using 8 parallel data lines in SDR (single data rate) mode • Supports single block, multi-block read and
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Chapter 49 Secured digital host controller (SDHC) • MMC 4-bit • MMC 8-bit • CE-ATA 1-bit • CE-ATA 4-bit • CE-ATA 8-bit • Identification mode (up to 400 kHz) • MMC full speed mode (up to 20 MHz) • MMC high speed mode (up to 52 MHz) • SD/SDIO full speed mode (up to 25 MHz) • SD/SDIO high speed mode (up to 50 MHz) 49.3 SDHC signal descriptions Table 49-1. SDHC signal descriptions Signal Description I/O SDHC_DCLK Generated clock used to drive the MMC, SD, SDIO or CE-ATA cards.
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Memory map and register definition Table 49-1. SDHC signal descriptions (continued) Signal SDHC_D6 Description I/O DAT6 line in 8-bit mode I/O Not used in other modes SDHC_D7 DAT7 line in 8-bit mode I/O Not used in other modes 49.4 Memory map and register definition This section includes the module memory map and detailed descriptions of all registers.
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Chapter 49 Secured digital host controller (SDHC) SDHC memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 400B_1030 Interrupt Status Register (SDHC_IRQSTAT) 32 R/W 0000_0000h 49.4.13/ 1405 400B_1034 Interrupt Status Enable Register (SDHC_IRQSTATEN) 32 R/W 117F_013Fh 49.4.14/ 1411 400B_1038 Interrupt Signal Enable Register (SDHC_IRQSIGEN) 32 R/W 0000_0000h 49.4.
PAGE 1384
Memory map and register definition SDHC_DSADDR field descriptions (continued) Field Description This register contains the 32-bit system memory address for a DMA transfer. Since the address must be word (4 bytes) align, the least 2 bits are reserved, always 0. When the SDHC stops a DMA transfer, this register points to the system address of the next contiguous data position. It can be accessed only when no transaction is executing (i.e. after a transaction has stopped).
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Chapter 49 Secured digital host controller (SDHC) SDHC_BLKATTR field descriptions (continued) Field Description When restoring transfer content prior to issuing a resume command, the host driver shall restore the previously saved block count. NOTE: Although the BLKCNT field is 0 after reset, the read of reset value is 0x1. This is because when XFERTYP[MSBSEL] bit is 0, indicating a single block transfer, the read value of BLKCNT is always 1. 0000h 0001h 0002h ...
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Memory map and register definition SDHC_CMDARG field descriptions Field Description 31–0 CMDARG Command Argument The SD/MMC command argument is specified as bits 39-8 of the command format in the SD or MMC specification.This register is write protected when the PRSSTAT[CDIHB0] bit is set. 49.4.4 Transfer Type Register (SDHC_XFERTYP) This register is used to control the operation of data transfers.
PAGE 1387
Chapter 49 Secured digital host controller (SDHC) Table 49-7. Transfer Type Register Setting for Various Transfer Types (continued) Multi/Single block select Block count enable Block count Function 1 0 Don't care Infinite transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The following table shows the relationship between the XFERTYP[CICEN] and XFERTYP[CCCEN], in regards to the XFERTYP[RSPTYP] as well as the name of the response type. Table 49-8.
PAGE 1388
Memory map and register definition Address: SDHC_XFERTYP is 400B_1000h base + Ch offset = 400B_100Ch Bit 31 30 29 28 27 26 25 24 23 22 0 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCEN DMAEN 0 0 0 CMDTYP W 0 R W Reset 0 0 0 0 0 0 0 0 0 0 DTDSEL 0 CMDINX MSBSEL Reset AC12EN 0 CCCEN 19 CICEN 20 DPSEL R 21 0 0 0 0 RSPTYP SDHC_XFERTYP field descriptions Field Description 31–30 Reserved
PAGE 1389
Chapter 49 Secured digital host controller (SDHC) SDHC_XFERTYP field descriptions (continued) Field Description This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: • Commands using only the CMD line (for example: CMD52). • Commands with no data transfer, but using the busy signal on DAT[0] line (R1b or R5b, for example: CMD38).
PAGE 1390
Memory map and register definition SDHC_XFERTYP field descriptions (continued) Field Description 0b 1b Write (host to card) Read (card to host) 3 Reserved This read-only field is reserved and always has the value zero. 2 AC12EN Auto CMD12 Enable Multiple block transfers for memory require a CMD12 to stop the transaction. When this bit is set to 1, the SDHC will issue a CMD12 automatically when the last block transfer has completed.
PAGE 1391
Chapter 49 Secured digital host controller (SDHC) 49.4.6 Command Response 1 (SDHC_CMDRSP1) This register is used to store part 1 of the response bits from the card.
PAGE 1392
Memory map and register definition Table 49-13. Response bit definition for each response type Response type Meaning of response Response field Response register R1,R1b (normal response) Card status R[39:8] CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2 (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2, CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4 (OCR register) OCR register for I/O etc.
PAGE 1393
Chapter 49 Secured digital host controller (SDHC) SDHC_CMDRSP3 field descriptions Field Description 31–0 CMDRSP3 Command Response 3 49.4.9 Buffer Data Port Register (SDHC_DATPORT) This is a 32-bit data port register used to access the internal buffer and it can not be updated in idle mode.
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Memory map and register definition Address: SDHC_PRSSTAT is 400B_1000h base + 24h offset = 400B_1024h Bit 31 30 29 28 27 26 25 24 DLSL R 23 22 21 20 19 18 17 0 CLSL 16 CINS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BREN BWEN RTA WTA SDOFF PEROFF HCKOFF IPGOFF SDSTB DLA CDIHB CIHB W 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 SDHC_PRSSTAT field descriptions Field 31–24 DLSL Descript
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Chapter 49 Secured digital host controller (SDHC) SDHC_PRSSTAT field descriptions (continued) Field Description The SYSCTL[RSTA] does not effect this bit.A software reset does not effect this bit. 0b 1b 15–12 Reserved 11 BREN This read-only field is reserved and always has the value zero. Buffer Read Enable This status bit is used for non-DMA read transfers. The SDHC may implement multiple buffers to transfer data efficiently. This read only flag indicates that valid data exists in the host side buffer.
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Memory map and register definition SDHC_PRSSTAT field descriptions (continued) Field Description During a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result of the stop at block gap request being set. This status is useful for the host driver in determining when to issue commands during write busy state.
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Chapter 49 Secured digital host controller (SDHC) SDHC_PRSSTAT field descriptions (continued) Field Description 0b 1b 3 SDSTB SD Clock Stable This status bit indicates that the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear SYSCTL[SDCLKEN] bit to remove glitch on the card clock when the frequency is changing.
PAGE 1398
Memory map and register definition SDHC_PRSSTAT field descriptions (continued) Field Description This status bit is generated if either the DLA or the RTA is set to 1. If this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command. Commands with a busy signal belong to CDIHB (e.g. R1b, R5b type). Except in the case when the command busy is finished, changing from 1 to 0 generates a transfer complete interrupt in the interrupt status register.
PAGE 1399
Chapter 49 Secured digital host controller (SDHC) Address: SDHC_PROCTL is 400B_1000h base + 28h offset = 400B_1028h Bit 31 30 29 28 27 0 23 22 21 20 19 18 17 16 RWCTL CREQ SABGREQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CDTL 0 0 0 R DMAS W Reset 0 0 0 0 0 0 0 0 EMODE 1 0 0 LCTL IABG 0 W D3CD Reset CDSS 0 WECINT 24 WECINS 25 WECRM R 26 DTW 0 0 0 SDHC_PROCTL field descriptions Field Descrip
PAGE 1400
Memory map and register definition SDHC_PROCTL field descriptions (continued) Field Description This bit is valid only in 4-bit mode, of the SDIO card, and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. Setting to 0 disables interrupt detection during a multiple block transfer. If the SDIO card can't signal an interrupt during a multiple block transfer, this bit should be set to 0 to avoid an inadvertent interrupt.
PAGE 1401
Chapter 49 Secured digital host controller (SDHC) SDHC_PROCTL field descriptions (continued) Field 9–8 DMAS Description DMA Select This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA operation. 00 01 10 11 7 CDSS Card Detect Signal Selection This bit selects the source for the card detection. 0b 1b 6 CDTL This is bit is enabled while the CDSS is set to 1 and it indicates card insertion. The SDHC supports all four endian modes in data transfer.
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Memory map and register definition SDHC_PROCTL field descriptions (continued) Field Description all these transactions. It is not necessary to change for each transaction. When the software issues multiple SD commands, setting the bit once before the first command is sufficient: it is not necessary to reset the bit between commands. 0b 1b LED off LED on 49.4.
PAGE 1403
Chapter 49 Secured digital host controller (SDHC) SDHC_SYSCTL field descriptions (continued) Field Description • • • • • • • • • • • • 0b 1b 25 RSTC 19–16 DTOCV No reset Reset Software Reset For ALL This reset effects the entire host controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization, the host driver shall set this bit to 1 to reset the SDHC.
PAGE 1404
Memory map and register definition SDHC_SYSCTL field descriptions (continued) Field Description Setting 00h bypasses the frequency prescaler of the SD Clock. Multiple bits must not be set, or the behavior of this prescaler is undefined. The two default divider values can be calculated by the frequency of SDHC clock and the following divisor bits.
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Chapter 49 Secured digital host controller (SDHC) SDHC_SYSCTL field descriptions (continued) Field Description • • • • • • 0b 1b 1 HCKEN Continue request is just set, or This bit is set, or Card insertion is detected, or Card removal is detected, or Card external interrupt is detected, or 80 clocks for initialization phase is ongoing SDHC clock will be internally gated off SDHC clock will not be automatically gated off System Clock Enable If this bit is set, system clock will always be active and no au
PAGE 1406
Memory map and register definition The table below shows the relationship between the CTOE and the CC bits. Table 49-19. SDHC status for CTOE/CC bit combinations Command complete Command timeout error Meaning of the status 0 0 X X 1 Response not received within 64 SDCLK cycles 1 0 Response received The table below shows the relationship between the Transfer Complete and the Data Timeout Error. Table 49-20.
PAGE 1407
Chapter 49 Secured digital host controller (SDHC) 27 26 25 0 w1c W 24 23 22 21 20 19 18 17 0 DCE CIE CCE CTOE 0 R 28 CEBE 29 DTOE 30 DEBE 31 DMAE Bit AC12E Address: SDHC_IRQSTAT is 400B_1000h base + 30h offset = 400B_1030h w1c w1c w1c w1c w1c w1c w1c w1c 16 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC CC 0 R W Reset 0 0 0 0 0 0 0 BRR DINT 0 BWR 0 CINS 0 CRM 0 CINT Reset BGE w1c w1c w1c
PAGE 1408
Memory map and register definition SDHC_IRQSTAT field descriptions (continued) Field Description 0b 1b 21 DCE Data CRC Error Occurs when detecting a CRC error when transferring read data, which uses the DAT line, or when detecting the Write CRC status having a value other than 010. 0b 1b 20 DTOE No Error Error No Error Error Data Timeout Error Occurs when detecting one of following time-out conditions.
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Chapter 49 Secured digital host controller (SDHC) SDHC_IRQSTAT field descriptions (continued) Field 15–9 Reserved 8 CINT Description This read-only field is reserved and always has the value zero. Card Interrupt This status bit is set when an interrupt signal is detected from the external card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD Clock to support wakeup.
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Memory map and register definition SDHC_IRQSTAT field descriptions (continued) Field Description 0b 1b 3 DINT DMA Interrupt Occurs only when the internal DMA finishes the data transfer successfully. Whenever errors occur during data transfer, this bit will not be set. Instead, the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring, this bit will be set.
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Chapter 49 Secured digital host controller (SDHC) 49.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN) Setting the bits in this register to 1 enables the corresponding interrupt status to be set by the specified event. If any bit is cleared, the corresponding interrupt status bit is also cleared (i.e. when the bit in this register is cleared, the corresponding bit in interrupt status register is always 0).
PAGE 1412
Memory map and register definition SDHC_IRQSTATEN field descriptions (continued) Field 24 AC12ESEN Description Auto CMD12 Error Status Enable 0b 1b Masked Enabled 23 Reserved This read-only field is reserved and always has the value zero.
PAGE 1413
Chapter 49 Secured digital host controller (SDHC) SDHC_IRQSTATEN field descriptions (continued) Field Description 0b 1b Masked Enabled 6 CINSEN Card Insertion Status Enable 5 BRRSEN Buffer Read Ready Status Enable 4 BWRSEN Buffer Write Ready Status Enable 3 DINTSEN DMA Interrupt Status Enable 2 BGESEN Block Gap Event Status Enable 0b 1b 0b 1b 0b 1b 0b 1b 0b 1b Masked Enabled Masked Enabled Masked Enabled Masked Enabled Masked Enabled 1 TCSEN Transfer Complete Status Enable 0 CCSEN
PAGE 1414
Memory map and register definition 49.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN) This register is used to select which interrupt status is indicated to the host system as the interrupt. These status bits all share the same interrupt line. Setting any of these bits to 1 enables interrupt generation. The corresponding status register bit will generate an interrupt when the corresponding interrupt signal enable bit is set.
PAGE 1415
Chapter 49 Secured digital host controller (SDHC) SDHC_IRQSIGEN field descriptions (continued) Field Description 0b 1b 20 DTOEIEN 19 CIEIEN 18 CEBEIEN 17 CCEIEN Masked Enabled Data Timeout Error Interrupt Enable 0b 1b Masked Enabled Command Index Error Interrupt Enable 0b 1b Masked Enabled Command End Bit Error Interrupt Enable 0b 1b Masked Enabled Command CRC Error Interrupt Enable 0b 1b Masked Enabled 16 CTOEIEN Command Timeout Error Interrupt Enable 15–9 Reserved This read-only field i
PAGE 1416
Memory map and register definition SDHC_IRQSIGEN field descriptions (continued) Field Description 0b 1b 2 BGEIEN Masked Enabled Block Gap Event Interrupt Enable 0b 1b Masked Enabled 1 TCIEN Transfer Complete Interrupt Enable 0 CCIEN Command Complete Interrupt Enable 0b 1b 0b 1b Masked Enabled Masked Enabled 49.4.
PAGE 1417
Chapter 49 Secured digital host controller (SDHC) • Check errors correspond to bits 1-4. • Set bits 1-4 corresponding to detected errors. • Clear bits 1-4 corresponding to detected errors. 3. Before reading the auto CMD12 error status bit 7. • Set bit 7 to 1 if there is a command that can't be issued. • Clear bit 7 if there is no command to issue. The timing for generating the auto CMD12 error and writing to the command register are asynchronous.
PAGE 1418
Memory map and register definition SDHC_AC12ERR field descriptions (continued) Field 7 CNIBAC12E Description Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12 error (D04-D01) in this register. 0b 1b 6–5 Reserved 4 AC12IE This read-only field is reserved and always has the value zero. Auto CMD12 Index Error Occurs if the command index error occurs in response to a command.
PAGE 1419
Chapter 49 Secured digital host controller (SDHC) 49.4.17 Host Controller Capabilities (SDHC_HTCAPBLT) This register provides the host driver with information specific to the SDHC implementation. The value in this register is the power-on-reset value, and does not change with a software reset. Any write to this register is ignored.
PAGE 1420
Memory map and register definition SDHC_HTCAPBLT field descriptions (continued) Field 23 SRS Description Suspend/Resume Support This bit indicates whether the SDHC supports suspend / resume functionality. If this bit is 0, the suspend and resume mechanism, as well as the read Wwait, are not supported, and the host driver shall not issue either suspend or resume commands.
PAGE 1421
Chapter 49 Secured digital host controller (SDHC) 49.4.18 Watermark Level Register (SDHC_WML) Both write and read watermark levels (FIFO threshold) are configurable. There value can range from 1 to 128 words. Both write and read burst lengths are also configurable. There value can range from 1 to 31 words.
PAGE 1422
Memory map and register definition Forcing a card interrupt will generate a short pulse on the DAT[1] line, and the driver may treat this interrupt as a normal interrupt. The interrupt service routine may skip polling the card interrupt factor as the interrupt is self cleared.
PAGE 1423
Chapter 49 Secured digital host controller (SDHC) SDHC_FEVT field descriptions (continued) Field Description Forces the IRQSTAT[DEBE] bit to be set. 21 DCE 20 DTOE 19 CIE 18 CEBE 17 CCE 16 CTOE 15–8 Reserved 7 CNIBAC12E 6–5 Reserved 4 AC12IE 3 AC12EBE 2 AC12CE 1 AC12TOE 0 AC12NE Force Event Data CRC Error Forces the IRQSTAT[DCE] bit to be set. Force Event Data Time Out Error Force the IRQSTAT[DTOE] bit to be set. Force Event Command Index Error Forces the IRQSTAT[CCE] bit to be set.
PAGE 1424
Memory map and register definition 49.4.20 ADMA Error Status Register (SDHC_ADMAES) When an ADMA error interrupt has occurred, the ADMA error states field in this register holds the ADMA state and the ADMA system address register holds the address around the error descriptor. For recovering from this error, the host driver requires the ADMA state to identify the error descriptor address as follows: • ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address.
PAGE 1425
Chapter 49 Secured digital host controller (SDHC) Address: SDHC_ADMAES is 400B_1000h base + 54h offset = 400B_1054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADMADCE ADMALME W 0 0 0 R ADMAES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDHC_ADMAES field descriptions Field 31–4 Reserved 3 ADMADCE Description This read-only field is reserved and alw
PAGE 1426
Memory map and register definition 49.4.21 ADMA System Address Register (SDHC_ADSADDR) This register contains the physical system memory address used for ADMA transfers.
PAGE 1427
Chapter 49 Secured digital host controller (SDHC) SDHC_VENDOR field descriptions Field Description 31–28 Reserved This read-only field is reserved and always has the value zero. 27–24 Reserved This read-only field is reserved and always has the value zero. 23–16 INTSTVAL Internal State Value 15–2 Reserved This read-only field is reserved and always has the value zero.
PAGE 1428
Memory map and register definition 49.4.23 MMC Boot Register (SDHC_MMCBOOT) This register contains the MMC fast boot control register.
PAGE 1429
Chapter 49 Secured digital host controller (SDHC) SDHC_MMCBOOT field descriptions (continued) Field Description 0011b 0100b 0101b 0110b 0111b ... 1110b 1111b SDCLK x 2^11 SDCLK x 2^12 SDCLK x 2^13 SDCLK x 2^14 SDCLK x 2^15 SDCLK x 2^22 Reserved 49.4.24 Host Controller Version (SDHC_HOSTVER) This register contains the vendor host controller version information. All bits are read only and will read the same as the power-reset value.
PAGE 1430
Functional description 49.5 Functional description The following sections provide a brief functional description of the major system blocks, including the data buffer, DMA crossbar switch interface, dual-port memory wrapper, data/command controller, clock & reset manager and clock generator. 49.5.
PAGE 1431
Chapter 49 Secured digital host controller (SDHC) • External DMA mode: • For a read operation, when there are more words received in the buffer than the amount set in the RDWML register, a DMA request is sent out to inform the external DMA to fetch the data. The request will be immediately de-asserted when there is an access on the DATPORT register. If the number of words in the buffer after the current burst meets or exceeds RDWML value, then the DMA request is asserted again.
PAGE 1432
Functional description System IP Bus or System AHB Bus SDHC Data buffer 31-24 23-16 23-16 15-8 7-0 15-8 7-0 31-24 Figure 49-28. Data swap between system bus and SDHC data buffer in byte little endian mode System IP Bus or System AHB Bus SDHC Data buffer 7-0 15-8 7-0 15-8 31-24 23-16 23-16 31-24 Figure 49-29. Data swap between system bus and SDHC data buffer in half word big endian mode 49.5.1.
PAGE 1433
Chapter 49 Secured digital host controller (SDHC) The SDHC will not start data transmission until the number of words set in the WML register can be held in the buffer. If the buffer is empty and the host system does not write data in time, the SDHC will stop the SD_CLK to avoid the data buffer under-run situation. 49.5.1.2 Read operation sequence There are three ways to read data from the buffer when the user transfers data to the card: 1. By using the external DMA through the SDHC DMA request signal 2.
PAGE 1434
Functional description maximum of 128 words. For both read and write, the burst length, can be from 1 word to the maximum of 31 words. The host driver may configure the value according to the system situation and requirement. During a multi-block data transfer, the block length may be set to any value between 1 and 4096 bytes inclusive which satisfies the requirements of the external card. The only restriction is from the external card.
PAGE 1435
Chapter 49 Secured digital host controller (SDHC) 544 Bytes WLAN Frame 802. .
PAGE 1436
Functional description Because the DMA burst length can't change during a data transfer for an external DMA transfer, the watermark level (read or write) must be a divisor of the block size. If it is not, transferring of the block may cause buffer under-run (read operation) or over-run (write operation). For example, if the block size is 512 bytes, the watermark level of read (or write) must be a power of two between 1 and 128.
PAGE 1437
Chapter 49 Secured digital host controller (SDHC) Crossbar switch interface Master Logic D MA Engine System Address R/W indication eSDHC Registers Error Indication Burst Length Data Exchange Buffer Control DMA Request Figure 49-31. DMA crossbar switch interface block 49.5.2.1 Internal DMA request If the watermark level requirement is met in data transfer, and the internal DMA is enabled, the data buffer block sends a DMA request to the crossbar switch interface.
PAGE 1438
Functional description starts, which is 31 bytes, more than 6 words. The host driver writer may take this variable burst length into account. It is also acceptable to configure the burst length as the divisor of the block size, so that each time the burst length will be the same. 49.5.2.3 Crossbar switch master interface It is possible that the internal DMA engine could fail during the data transfer.
PAGE 1439
Chapter 49 Secured digital host controller (SDHC) • Valid/Invalid descriptor. • Nop descriptor. • Set data length descriptor. • Set data address descriptor. • Link descriptor. • Interrupt flag and end flag in descriptor. For ADMA2, including the following descriptors: • Valid/Invalid descriptor. • Nop descriptor. • Rsv descriptor. • Set data length & address descriptor. • Link descriptor. • Interrupt flag and end flag in descriptor. ADMA2 deals with the lower 32-bit first, and then the higher 32-bit.
PAGE 1440
Functional description Table 49-35. Format of the ADMA1 descriptor table (continued) Act2 Act1 Symbol Comment 0 0 nop No operation 0 1 set Set data length 1 0 tran Transfer data Data address 1 1 link Link descriptor Descriptor address Valid 31-28 27-12 Don't care 0000 Data length Valid = 1 indicates this line of descriptor is effective. If Valid = 0 generate ADMA error Interrupt and stop ADMA. End End = 1 indicates current descriptor is the ending one.
PAGE 1441
Chapter 49 Secured digital host controller (SDHC) Table 49-36. Format of the ADMA2 descriptor table (continued) Valid Valid = 1 indicates this line of descriptor is effective. If valid = 0 generate ADMA error interrupt and stop ADMA. End End = 1 indicates current descriptor is the ending one. Int Int = 1 generates DMA interrupt when this descriptor is done.
PAGE 1442
Functional description 49.5.2.4.3 ADMA error The ADMA stops whenever any error is encountered. These errors include: • Fetching descriptor error • Transfer error • Data length mismatch error ADMA descriptor error will be generated when it fails to detect 'valid' flag in the descriptor. If ADMA descriptor error occurs, the interrupt is not generated even if the 'interrupt' flag of this descriptor is set.
PAGE 1443
Chapter 49 Secured digital host controller (SDHC) 2. SD clock and monitor. 3. Command agent. 4. Data agent. 49.5.3.1 SD transceiver In the SD protocol unit, the transceiver is the main control module. It consists of a FSM and control module, from which the control signals for all other three modules are generated. 49.5.3.2 SD clock & monitor This module monitors the signal level on all 8 data lines, the command lines, and directly routes the level values into the register bank.
PAGE 1444
Functional description CLR_CRC ZERO CRC_IN CRC Bus [0] CRC Bus [1] CRC Bus [2] CRC Bus [3] CRC Bus [4] CRC Bus [5] CRC Bus [6] CRC OUT Figure 49-34. Command CRC Shift Register The CRC polynomials for the CMD are as follows: Generator polynomial: G(x) = x7 + x3 + 1 M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0 CRC[6:0] = Remainder [(M(x) * x7) / G(x)] 49.5.3.4 Data agent The data agent deals with the transactions on the eight data lines.
PAGE 1445
Chapter 49 Secured digital host controller (SDHC) 1. Bus clock. 2. SDHC clock. 3. System clock. The module monitors the activities of all other modules, supplies the clocks for them, and when enabled, automatically gates off the corresponding clocks. 49.5.5 Clock generator The clock generator generates the SDHC_CLK by peripheral source clock in two stages. The following diagram illustrates the structure of the divider. The term "base" represents the frequency of peripheral source clock.
PAGE 1446
Functional description 49.5.6.2 Interrupt in 4-bit mode Since the interrupt and data line 1 share Pin 8 in 4-bit mode, an interrupt will only be sent by the card and recognized by the host during a specific time. This is known as the interrupt period. The SDHC will only sample the level on pin 8 during the interrupt period. At all other times, the host will ignore the level on pin 8, and treat it as the data signal.
PAGE 1447
Chapter 49 Secured digital host controller (SDHC) SDIO interrupt status latched in the SDHC and to stop driving the interrupt signal to the system interrupt controller. The host driver must issue a CMD52 to clear the card interrupt. After completion of the card interrupt service, the SDIO Interrupt Enable bit is set to 1, and the SDHC starts sampling the interrupt signal again.
PAGE 1448
Functional description detection or not, the CD pin is always a reference for card detection. Whether the DAT[3] pin or the CD pin is used to detect card insertion, the SDHC will send an interrupt (if enabled) to inform the Host system that a card is inserted. 49.5.8 Power management and wakeup events When there is no operation between the SDHC and the card through the SD bus, the user can completely disable the bus clock and SDHC clock in the chip level clock control module to save power.
PAGE 1449
Chapter 49 Secured digital host controller (SDHC) • No read or write transfer is active • Data and command lines are not active • No interrupts are pending • Internal data buffer is empty 49.5.9 MMC fast boot In Embedded MultiMediaCard(eMMC4.3) spec, add fast boot feature need hardware support.
PAGE 1450
Functional description Boot operation will be terminated when all contents of the enabled boot data are sent to the master. After boot operation is executed, the slave shall be ready for CMD1 operation and the master needs to start a normal MMC initialization sequence by sending CMD1.
PAGE 1451
Chapter 49 Secured digital host controller (SDHC) CLK CMD CMD01 CMD0/Reset S DAT[0] Min 74 clocks required after power is stable to start boot command NOTE 1. 010 E S 512bytes +CRC E S 512bytes +CRC CMD1 RESP CMD2 RESP CMD3 RESP E 50ms max 1 sec.max CMD0 with argument 0xFFFFFFFA Figure 49-38. MultiMediaCard state diagram (alternative boot mode) 49.6 Initialization/application of SDHC All communication between system and cards are controlled by the host.
PAGE 1452
Initialization/application of SDHC set BCEN bit; if (auto12 command is to use) set AC12EN bit; } } write_reg(CMDARG, ); // configure the command argument write_reg(XFERTYP, wCmd); // set Transfer Type register as wCmd value to issue the command } wait_for_response(cmd_index) { while (CC bit in IRQ Status register is not set); // wait until Command Complete bit is set read IRQ Status register and check if any error bits about Command are set if (any error bits are set) report error; write 1 to clea
PAGE 1453
Chapter 49 Secured digital host controller (SDHC) Enable card detection irq (1) Wait SDHC interrupt No card presents Check IRQSTAT[CINS] Y es, card presents Clear CINSIEN to disable card detection irq (2) Voltage validation Figure 49-39.
PAGE 1454
Initialization/application of SDHC • Software reset (host only) is proceed by the write operation on the SYSCTL[RSTD], SYSCTL[RSTC], or SYSCTL[RSTA] bits to reset the data part, command part, or all parts of the host controller, respectively • Card reset (card only). The command, "Go_Idle_State" (CMD0), is the software reset command for all types of MMC cards, SD Memory cards, and CE-ATA cards. This command sets each card into the idle state regardless of the current card state.
PAGE 1455
Chapter 49 Secured digital host controller (SDHC) 49.6.2.3 Voltage validation All cards should be able to establish communication with the host using any operation voltage in the maximum allowed voltage range specified in the card specification. However, the supported minimum and maximum values for VDD are defined in the Operation Conditions Register (OCR) and may not cover the whole range.
PAGE 1456
Initialization/application of SDHC return; // } // end of if (no error ... else if (errors other than time-out occur) { // command/response pair is corrupted deal with it by program specific manner; } // of else if (response time-out else { // CMD55 is refuse, it must be MMC card or CE-ATA card if (card is already labelled as SDCombo) { // change label re-label the card as SDIO; ignore the error or report it; return; // card is identified as SDIO card } // of if (card is ...
PAGE 1457
Chapter 49 Secured digital host controller (SDHC) For MMC operation, the host starts the card identification process in open-drain mode with the identification clock rate lower than 400 kHz and the power voltage higher than 2.7 V. The open drain driver stages on the CMD line allow parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions (CMD1).
PAGE 1458
Initialization/application of SDHC 49.6.3.1 Block write This section discusses the block write access methods. 49.6.3.1.1 Normal write During a block write (CMD24 - 27, CMD60, CMD61), one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. If the CRC fails, the card shall indicate the failure on the dat line.
PAGE 1459
Chapter 49 Secured digital host controller (SDHC) The software flow to write to a card incorporates the internal DMA and the write operation is a multi-block write with the Auto CMD12 enabled. For the other two methods (by means of external DMA or CPU polling status) with different transfer methods, the internal DMA parts should be removed and the alternative steps should be straightforward. The software flow to write to a card is described below: 1.
PAGE 1460
Initialization/application of SDHC 1. Check the card status, wait until card is ready for data. 2. Set the card block length/size: a. For SD/MMC, use SET_BLOCKLEN (CMD16) b. For SDIO cards or the I/O portion of SDCombo cards, use IO_RW_DIRECT(CMD52) to set the I/O Block Size bit field in the CCCR register (for function 0) or FBR register (for functions 1~7) c. For CE-ATA cards, configure bits 1~0 in the scrControl register 3.
PAGE 1461
Chapter 49 Secured digital host controller (SDHC) When the write operation is paused, the data transfer inside the host system is not stopped, and the transfer is active until the data buffer is full. Because of this (if not needed), it is recommended to avoid using the suspend command for the SDIO card. This is because when such a command is sent, the SDHC thinks the system will switch to another function on the SDIO card, and flush the data buffer.
PAGE 1462
Initialization/application of SDHC 3. Set the SDHC block length register to be the same as the block length set for the card in Step 2. 4. Set the SDHC number block register (NOB), nob is 5 (for instance). 5. Disable the buffer read ready interrupt, configure the DMA settings and enable the SDHC DMA when sending the command with data transfer. The XFERTYP[AC12EN] bit should also be set: 6. Wait for the transfer complete interrupt. 7.
PAGE 1463
Chapter 49 Secured digital host controller (SDHC) 5. Set the SDHC block length register to be the same as the block length set for the card in Step 2. 6. Set the SDHC number block register (NOB), nob is 5 (for instance). 7. Disable the buffer read ready interrupt, configure the DMA setting and enable the eSDHC DMA when sending the command with data transfer. The AC12EN bit should also be set 8. Set the SABGREQ bit. 9. Wait for the Transfer Complete interrupt. 10. Clear the SABGREQ bit. 11.
PAGE 1464
Initialization/application of SDHC 49.6.3.3.1 Suspend After setting the PROCTL[SABGREQ] bit, the host driver may send a suspend command to switch to another function of the SDIO card. The SDHC does not monitor the content of the response, so it doesn't know if the suspend command succeeded or not. Accordingly, it doesn't de-assert read wait for read pause. To solve this problem, the driver shall not mark the suspend command as a "suspend", (i.e. setting the XFERTYP[CMDTYP] bits to 01).
PAGE 1465
Chapter 49 Secured digital host controller (SDHC) 49.6.3.4 ADMA usage To use the ADMA in a data transfer, the host driver must prepare the correct descriptor chain prior to sending the read/write command. The steps to accomplish this are: 1. Create a descriptor to set the data length that the current descriptor group is about to transfer. The data length should be even numbers of the block size. 2. Create another descriptor to transfer the data from the address setting in this descriptor.
PAGE 1466
Initialization/application of SDHC last block is not transferred. On the other hand, if it is within the last block that the CRC error occurs, an auto CMD12 will be sent by the SDHC. In this case, the driver shall resend or re-obtain the last block with a single block transfer. 49.6.3.5.2 Internal DMA error During the data transfer with internal simple DMA, if the DMA engine encounters some error on the system bus, the DMA operation is aborted and DMA error interrupt is sent to the host system.
PAGE 1467
Chapter 49 Secured digital host controller (SDHC) 2. Invalid descriptor error: For such errors, it is recommended to retrieve the transfer context, reset for the data part and re-create the descriptor chain from the invalid descriptor and issue a new transfer. As the data to transfer now may be less than the previous setting, the data length configured in the new descriptor chain should match the new value. 3. Data-length mismatch error: It is similar to recover from this error.
PAGE 1468
Initialization/application of SDHC When the SDIO interrupt is captured by the SDHC, and the host system is informed by the SDHC asserting the SDHC interrupt line, the interrupt service from the host driver is called. As the interrupt factor is controlled by the external card, the interrupt from the SDIO card must be served before the IRQSTAT[CINT] bit is cleared by written 1. Refer to Card interrupt handling for the card interrupt handling flow. 49.6.
PAGE 1469
Chapter 49 Secured digital host controller (SDHC) send CMD52 to clear bit EHS at address 0x13 and read after write to confirm EHS bit is cleared; change clock divisor value or configure the system clock feeding into eSDHC to generate the card_clk of the desired value below 25MHz; (data transactions like normal peers) } 49.6.4.
PAGE 1470
Initialization/application of SDHC if (HS_TIMING is not 0) report the function switch failed and return; change clock divisor value or configure the system clock feeding into eSDHC to generate the card_clk of the desired value below 20MHz; (data transactions like normal peers) } 49.6.4.
PAGE 1471
Chapter 49 Secured digital host controller (SDHC) 49.6.5.2 ADMA2 operation Set_adma2_descriptor { if (to start data transfer) { // Make sure the address is 32-bit boundary (lower 2-bit are always '00'). Set higher 32-bit of descriptor for this data transfer initial address; Set [31:16] bits data length (byte unit); Set Act bits to '10'; } else if (to fetch descriptor at non-continuous address) { Set Act bits to '11'; // Make sure the address is 32-bit boundary (lower 2-bit are always set to '00').
PAGE 1472
Initialization/application of SDHC 6. Software need to configure XFERTYP register to start the boot process . In normal boot mode, XFERTYP[CMDINX], XFERTYP[CMDTYP], XFERTYP[RSPTYP], XFERTYP[CICEN], XFERTYP[CCCEN], XFERTYP[AC12EN], XFERTYP[BCEN] and XFERTYP[DMAEN] are kept default value. XFERTYP[DPSEL] bit is set to 1, XFERTYP[DTDSEL] is set to 1, XFERTYP[MSBSEL] is set to 1. Note XFERTYP[DMAEN] should be configured as 0 in polling mode.
PAGE 1473
Chapter 49 Secured digital host controller (SDHC) is set to 1, DTDSEL is set to 1, MSBSEL is set to 1. Note DMAEN should be configured as 0 in polling mode. And if BCEN is configured as 1 in polling mode, better to configure blk no in Bock Attributes Register to the max value. 7. When the step 6 is configured, boot process will begin. Software need to poll the data buffer ready status to read the data from buffer in time.
PAGE 1474
Initialization/application of SDHC 3. Software then need to configure BLKATTR register to set block size/no. In DMA mode, it is better to set block number to the max value(16'hffff). 4. Software need to configure PROCTL[DTW]. 5. Software enable ADMA2 by configuring PROCTL[DMAS]. 6. Software need to set at least three pairs ADMA2 descriptor in boot memory (ie, in IRAM, at least 6 words). The first pair descriptor define the start address (ie, IRAM) and data length(ie,512byte*VALUE1) of first part boot code.
PAGE 1475
Chapter 49 Secured digital host controller (SDHC) stop at block gap when card block counter is equal to this value. And need to configure MMCBOOT[DTOCVACK] bit to select the ack timeout value according to the sd clk frequence. 12. Software need to clear IRQSTAT[TC] and IRQSTAT[BGE] bit. And software need to clear PROCTL[SABGREQ], and set PROCTL[CREQ] to 1 to resume the data transfer. Host will transfer the VALUE2 and VAULE3 data to the destination that is set by descriptor. 13.
PAGE 1476
Initialization/application of SDHC Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation Description CMD1 bcr [31:0] OCR without busy R3 SEND_OP_COND Asks all MMC and SD memory cards in idle state to send their operation conditions register contents in the response on the CMD line. CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line.
PAGE 1477
Chapter 49 Secured digital host controller (SDHC) Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation Description CMD8 adtc [31:0] stuff bits R1 SEND_EXT_CSD The card sends its EXT_CSD register as a block of data, with a block size of 512 bytes. CMD9 ac [31:6] RCA R2 SEND_CSD Addressed card sends its card-specific data (CSD) on the CMD line. R2 SEND_CID Addressed card sends its card-identification (CID) on the CMD line.
PAGE 1478
Initialization/application of SDHC Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation Description CMD25 adtc [31:0] data address R1 WRITE_MULTIPLE_BL Continuously writes blocks of OCK data until a STOP_TRANSMISSION follows. CMD26 adtc [31:0] stuff bits R1 PROGRAM_CID Programming of the card identification register. This command shall be issued only once per card.
PAGE 1479
Chapter 49 Secured digital host controller (SDHC) Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation CMD36 ac [31:0] data address R1 TAG_ERASE_GROUP Sets the address of the last _END erase group within a continuous range to be selected for erase. CMD37 ac [31:0] data address R1 UNTAG_ERASE_GRO Removes one previously UP selected erase group from the erase selection.
PAGE 1480
Initialization/application of SDHC Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation Description CMD56 adtc [31:1] stuff bits R1b GEN_CMD Used either to transfer a data block to the card or to get a data block from the card for general purpose / application specific commands. The size of the data block is set by the SET_BLOCK_LEN command.
PAGE 1481
Chapter 49 Secured digital host controller (SDHC) Table 49-37. Commands for MMC/SD/SDIO/CE-ATA cards (continued) CMD INDEX Type Argument Resp Abbreviation Description ACMD5110 adtc [31:0] stuff bits R1 SEND_SCR Reads the SD Configuration Register (SCR). 1. CMD3 differs for MMC and SD cards. For MMC cards, it is referred to as SET_RELATIVE_ADDR, with a response type of R1. For SD cards, it is referred to as SEND_RELATIVE_ADDR, with a response type of R6 (with RCA inside). 2.
PAGE 1482
Software restrictions 49.7.1 Initialization active The driver cannot set SYSCTL[INITA] bit when any of the command line or data lines is active, so the driver must ensure both PRSSTAT[CDIHB] and PRSSTAT[CIHB] bits are cleared. And in order to auto clear the SYSCTL[INITA] bit, the SYSCTL[SDCLKEN] bit must be '1', otherwise no clocks can go out to the card and SYSCTL[INITA] will never clear. 49.7.
PAGE 1483
Chapter 49 Secured digital host controller (SDHC) 49.7.5 (A)DMA address setting To configure ADMA1/ADMA2/DMA address register, when TC[IRQSTAT] bit is set, the register will always update itself with the internal address value to support dynamic address synchronization, so software must make sure TC[IRQSTAT] bit is cleared prior to configuring ADMA1/ADMA2/DMA address register. 49.7.6 Data port access Data port does not support parallel access.
PAGE 1484
Software restrictions K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1484 Freescale Semiconductor, Inc.
PAGE 1485
Chapter 50 Integrated interchip sound (I2S) 50.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section discusses the architecture, the programming model, the operating modes, and initialization of integrated interchip sound (I2S) module. The I2S is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices.
PAGE 1486
Introduction 50.1.1 Block diagram The following figure illustrates the organization of the I2S. It consists of control registers to set up the port, status register, separate transmit and receive circuits with FIFO registers, and separate serial clock and frame sync generation for the transmit and receive sections. The second set of Tx and Rx FIFOs replicates the logic used for the first set of FIFOs.
PAGE 1487
Chapter 50 Integrated interchip sound (I2S) • Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots • Gated clock mode operation requiring no frame sync • 2 sets of transmit and receive FIFOs. Each of the four FIFOs is 15x32 bits.
PAGE 1488
Introduction • Asynchronous protocol • Synchronous protocol • Gated clock mode • Synchronous protocol only • I2S mode • AC97 mode • AC97 fixed mode (ACNT[FV] = 0) • AC97 variable mode (ACNT[FV] = 1) These modes can be programmed by several bits in the I2S control registers. The following table lists these operating modes and some of the typical applications in which they can be used: Table 50-1.
PAGE 1489
Chapter 50 Integrated interchip sound (I2S) The I2S supports both normal and network modes, and these can be selected independently of whether the transmitter and receiver are synchronous or asynchronous. Typically, these protocols are used in a periodic manner, where data transfers at regular intervals, such as at the sampling rate of an external codec. Both modes use the concept of a frame. The beginning of the frame is marked with a frame sync when programmed with continuous clock.
PAGE 1490
I2S signal descriptions Table 50-2. I2S signal descriptions (continued) Signal Description I/O SRFS Serial receive frame Sync. The SRFS port can be used as an input or output. The frame sync is used by the receiver to synchronize the transfer of data. The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. If SRFS is configured as an input, the external device should drive SRFS during the rising edge of STCK or SRCK.
PAGE 1491
Chapter 50 Integrated interchip sound (I2S) I2S STXD SRXD STCK STFS SRCK SRFS I2S internal continuous clock for TX/RX (RCR[RXDIR] = 1,TCR[TXDIR] = 1, RCR[RFDIR] = 1,TCR[TFDIR] = 1, CR[SYN] = 0) I2S STXD SRXD STCK STFS SRCK SRFS I2S external continuous clock for TX/RX (RCR[RXDIR] = 0,TCR[TXDIR] = 0, RCR[RFDIR] = 0,TCR[TFDIR] = 0, CR[SYN] = 0) I2S STXD SRXD STCK STFS SRCK SRFS I2S internal continuous clock for RX (RCR[RXDIR] = 1, TCR[TXDIR] = 0, RCR[RFDIR] = 1,TCR[TFDIR] = 0, CR[SYN] = 0) I2S external cont
PAGE 1492
I2S signal descriptions (not used in gated clock) Continuous STCK, SRCK STFS, SRFS Early STFS, SRFS Gated STCK STXD 7 6 4 5 3 2 1 0 7 6 2 1 0 7 6 8-bit Data SRXD 7 6 5 4 3 Bit-length frame sync Word-length frame sync Figure 50-3. Serial clock and frame sync timing The following table shows a list of clock pin configurations. Table 50-3.
PAGE 1493
Chapter 50 Integrated interchip sound (I2S) Table 50-3.
PAGE 1494
Memory map/register definition I2S memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_F018 I2S Interrupt Enable Register (I2S0_IER) 32 R/W 0000_3003h 50.3.7/ 1505 4002_F01C I2S Transmit Configuration Register (I2S0_TCR) 32 R/W 0000_0200h 50.3.8/ 1509 4002_F020 I2S Receive Configuration Register (I2S0_RCR) 32 R/W 0000_0200h 50.3.9/ 1511 4002_F024 I2S Transmit Clock Control Registers (I2S0_TCCR) 32 R/W 0004_0000h 50.3.
PAGE 1495
Chapter 50 Integrated interchip sound (I2S) 50.3.1 I2S Transmit Data Registers 0 (I2Sx_TX0) The TX0 registers store the data to be transmitted by the I2S.
PAGE 1496
Memory map/register definition I2Sx_TX1 field descriptions (continued) Field Description Example: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you write Data1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded. NOTE: Enable I2S (CR[I2SEN]=1) before writing to the I2S transmit data registers. 50.3.
PAGE 1497
Chapter 50 Integrated interchip sound (I2S) I2Sx_RX1 field descriptions (continued) Field Description FIFOs are in use, data is transferred to each data register alternately. RX1 can only be used in twochannel mode of operation. 50.3.5 I2S Control Register (I2Sx_CR) The I2S Control Register (CR) sets up the I2S. I2S reset is controlled by bit 0 in the CR. I2S operating modes are also selected in this register (except AC97 mode which is selected in the ACNT register).
PAGE 1498
Memory map/register definition I2Sx_CR field descriptions (continued) Field Description This bit provides the option to keep the frame-sync and clock enabled or to disable them after the receive frame in which the receiver is disabled. Writing to this bit has effect only when CR[RE] is disabled.The receiver is disabled by clearing the CR[RE] bit. 0 1 10 TFRCLKDIS Transmit Frame Clock Disable.
PAGE 1499
Chapter 50 Integrated interchip sound (I2S) I2Sx_CR field descriptions (continued) Field Description 10 11 4 SYN Synchronous Mode. This bit controls whether I2S is in synchronous mode or not. In synchronous mode, the transmit and receive sections of I2S share a common clock port (STCK) and frame sync port (STFS). 0 1 3 NET This bit controls whether I2S is in network mode or not. Network mode not selected. Network mode selected. Receive Enable. Enables the receive section of the I2S.
PAGE 1500
Memory map/register definition I2Sx_CR field descriptions (continued) Field Description This bit is used to enable/disable the I2S. When disabled, all I2S status bits are preset to the same state produced by the power-on reset, all control bits are unaffected, the contents of Tx and Rx FIFOs are cleared. When I2S is disabled, all internal clocks are disabled (except register access clock). 0 1 I2S is disabled. I2S is enabled. 50.3.
PAGE 1501
Chapter 50 Integrated interchip sound (I2S) I2Sx_ISR field descriptions Field 31–25 Reserved 24 RFRC Description This read-only field is reserved and always has the value zero. Receive Frame Complete. This flag is set at the end of the frame during which receiver is disabled. If receive frame and clock are not disabled in the same frame, this flag is also set at the end of the frame in which receive frame and clock are disabled.
PAGE 1502
Memory map/register definition I2Sx_ISR field descriptions (continued) Field Description This flag bit is set when RX1 or Rx FIFO 1 is loaded with a new value and two-channel mode is selected. RDR1 is cleared when the core reads the RX1 register. If Rx FIFO 1 is enabled, RDR1 is cleared when the FIFO is empty.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_ISR field descriptions (continued) Field Description This flag is set when the RXSR is filled and ready to transfer to RX0 register or to Rx FIFO 0 (when enabled) and these are already full. If Rx FIFO 0 is enabled, this is indicated by RFF0 flag, else this is indicated by the RDR0 flag. The RXSR is not transferred in this case. The ROE0 flag causes an interrupt if IER[RIE] and IER[ROE0EN] are set. The ROE0 bit is cleared by POR and I2S reset.
PAGE 1504
Memory map/register definition I2Sx_ISR field descriptions (continued) Field 5 TLS Description Transmit Last Time Slot. This flag indicates the last time slot in a frame. When set, it indicates that the current time slot is the last time slot of the frame. TLS is set at the start of the last transmit time slot and causes the I2S to issue an interrupt (if IER[TIE] and TLSEN are set). TLS is not generated when frame rate is 1 in normal mode of operation.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_ISR field descriptions (continued) Field Description 0 TFE0 Transmit FIFO Empty 0. This flag is set when the empty slots in Tx FIFO exceed or are equal to the selected Tx FIFO WaterMark 0 (TFWM0) threshold. The setting of TFE0 only causes an interrupt when IER[TIE] and IER[TFE0EN] are set and Tx FIFO0 is enabled. The TFE0 bit is automatically cleared when the data level in Tx FIFO0 becomes more than the amount specified by the watermark bits.
PAGE 1506
Memory map/register definition I2Sx_IER field descriptions (continued) Field Description 0 1 22 RDMAE Receive DMA Enable. This bit allows I2S to request for DMA transfers. When enabled, DMA requests are generated when any of the RFF0/1 bits in the ISR are set and if the corresponding RFEN bit is also set. If the corresponding FIFO is disabled, a DMA request is generated when the corresponding RDR bit is set. 0 1 21 RIE This control bit allows the I2S to issue receiver related interrupts to the core.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_IER field descriptions (continued) Field Description Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not. 0 1 14 RDR0EN Enable Bit. Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not. 0 1 13 TDE1EN Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
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Memory map/register definition I2Sx_IER field descriptions (continued) Field Description 0 1 6 RFSEN Enable Bit. Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not. 0 1 5 TLSEN Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not. Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
PAGE 1509
Chapter 50 Integrated interchip sound (I2S) 50.3.8 I2S Transmit Configuration Register (I2Sx_TCR) The TCR directs the transmit operation of the I2S. A power-on reset clears all TCR bits. However, I2S reset does not affect the TCR bits.
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Memory map/register definition I2Sx_TCR field descriptions (continued) Field 5 TXDIR Description Transmit clock direction This bit controls the direction and source of the clock signal used to clock the TXSR. Internally generated clock is output through the STCK port. External clock is taken from this port. 0 1 4 TSHFD Transmit clock is external. Transmit clock generated internally Transmit Shift Direction. This bit controls whether the MSB or LSB will be transmitted first in a sample.
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Chapter 50 Integrated interchip sound (I2S) 50.3.9 I2S Receive Configuration Register (I2Sx_RCR) RCR directs the receive operation of the I2S. A power-on reset clears all RCR bits. However, I2S reset does not affect the RCR bits.
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Memory map/register definition I2Sx_RCR field descriptions (continued) Field Description This bit controls the direction and source of the receive frame sync signal. Internally generated frame sync signal is sent out through the SRFS port and external frame sync is taken from the same port. 0 1 5 RXDIR Receive Clock Direction. This bit controls the direction and source of the clock signal used to clock the RXSR. Internally generated clock is output through the SRCK port.
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Chapter 50 Integrated interchip sound (I2S) 50.3.10 I2S Transmit Clock Control Registers (I2Sx_TCCR) The I2S Transmit and Receive Control (TCCR and RCCR) registers are 19-bit, read/write control registers used to direct the operation of the I2S. The Clock and Reset Module (CRM) can source the I2S clock (network clock) from multiple sources and perform fractional division to support commonly used audio bit rates.
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Memory map/register definition I2Sx_TCCR field descriptions (continued) Field Description control the amount of valid data in those 32 bits. In AC97 Mode of operation, if word length is set to any value other than 16 bits, it will result in a word length of 20 bits. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 12–8 DC Reserved. Do not program this value. Reserved. Do not program this value. Reserved. Do not program this value. 8 10 12 Reserved.
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Chapter 50 Integrated interchip sound (I2S) 50.3.11 I2S Receive Clock Control Registers (I2Sx_RCCR) The I2S Transmit and Receive Control (TCCR and RCCR) registers are 19-bit, read/write control registers used to direct the operation of the I2S. The Clock and Reset Module (CRM) can source the I2S clock (network clock) from multiple sources and perform fractional division to support commonly used audio bit rates.
PAGE 1516
Memory map/register definition I2Sx_RCCR field descriptions (continued) Field Description used to control the amount of valid data in those 32 bits. In AC97 Mode of operation, if word length is set to any value other than 16 bits, it will result in a word length of 20 bits. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 12–8 DC Number of Bits/Word: 2; Supported in Implementation: No. Number of Bits/Word: 4; Supported in Implementation: No.
PAGE 1517
Chapter 50 Integrated interchip sound (I2S) Table 50-40.
PAGE 1518
Memory map/register definition I2Sx_FCSR field descriptions (continued) Field Description 1100 1101 1110 1111 27–24 TFCNT1 Transmit FIFO Counter1. These bits indicate the number of data words in Transmit FIFO. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 23–20 RFWM1 12 data word in receive FIFO. 13 data word in receive FIFO. 14 data word in receive FIFO. 15 data word in receive FIFO. 0 data word in transmit FIFO. 1 data word in transmit FIFO.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_FCSR field descriptions (continued) Field Description 1010 1011 1100 1101 1110 1111 19–16 TFWM1 Transmit FIFO Empty WaterMark 1. These bits control the threshold at which the TFE1 flag will be set. The TFE1 flag is set whenever the empty slots in Tx FIFO exceed or are equal to the selected threshold.
PAGE 1520
Memory map/register definition I2Sx_FCSR field descriptions (continued) Field Description These bits indicate the number of data words in Receive FIFO 0. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1000 1001 1010 1011 1100 1101 1110 1111 11–8 TFCNT0 Transmit FIFO Counter 0. These bits indicate the number of data words in Transmit FIFO 0. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7–4 RFWM0 0 data word in receive FIFO. 1 data word in receive FIFO.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_FCSR field descriptions (continued) Field Description 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 3–0 TFWM0 RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....
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Memory map/register definition I2Sx_FCSR field descriptions (continued) Field Description 1001 TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO ≤ 6 data. TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO ≤ 5 data. TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO ≤ 4 data.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_ACNT field descriptions (continued) Field Description This bit specifies whether the next frame will carry an AC97 Write Command or not. The programmer should take care that only one of the bits (WR or RD) is set at a time. When this bit is set, the corresponding tag bits (corresponding to Command Address and Command Data slots of the next Tx frame) are automatically set. This bit is automatically cleared by the I2S after completing transmission of a frame.
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Memory map/register definition I2Sx_ACADD field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–0 ACADD AC97 Command Address. These bits store the Command Address Slot information (bit 19 of the slot is sent in accordance with the Read and Write Command bits in ACNT register). These bits can be updated by a direct write from the Core. They are also updated with the information received in the incoming Command Address Slot.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_ATAG field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 ATAG AC97 Tag Value. Writing to this register (by the Core) sets the value of the Tx-Tag in AC97 fixed mode of operation. On a read, the Core gets the Rx-Tag Value received (in the last frame) from the Codec. If TIF bit in ACNT register is set, the TAG value is also stored in Rx-FIFO in addition to ATAG register.
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Memory map/register definition I2Sx_RMSK field descriptions Field Description 31–0 RMSK Receive Mask. These bits indicate which slot has been masked in the current frame. The Core can write to this register to control the time slots in which the I2S receives data. Each bit has info corresponding to the respective time slot in the frame. RMSK register value must be set before enabling Receiver.Receive mask bits should not be used in I2S Slave mode of operation. 0 1 Valid Time Slot.
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Chapter 50 Integrated interchip sound (I2S) I2Sx_ACCEN field descriptions Field Description 31–10 Reserved This read-only field is reserved and always has the value zero. 9–0 ACCEN AC97 Channel Enable. The Core writes a `1' to these bits to enable an AC97 data channel. Writing a `0' has no effect. Bit [0] corresponds to the first data slot in an AC97 frame (Slot #3) and Bit [9] corresponds to the tenth data slot (slot #12). Writes to these bits only have effect in the AC97 Variable mode of operation.
PAGE 1528
Functional description 50.4.1 Detailed operating mode descriptions The following sections provide detailed descriptions of the above modes. 50.4.1.1 Normal mode Normal mode is the simplest mode of the I2S. It transfers data in one time slot per frame. A time slot is a unit of data and the RCCR[WL] bits define the number of bits in a time slot. In continuous clock mode, a frame sync occurs at the beginning of each frame.
PAGE 1529
Chapter 50 Integrated interchip sound (I2S) • In gated-external mode, the data word in transmitted on the external clock. • In gated-internal mode, the data word is transmitted whenever data is available in the transmit FIFO. If transmit FIFO 0 is not enabled and the transmit data register empty enable (IER[TDE0EN]) and transmit interrupt enable (IER[TIE]) bits are set, transmit interrupt 0 occurs when the word in I2S_TX0 is shifted to transmit shift (TXSR) register.
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Functional description If receive FIFO 0 is enabled and receive interrupt enable (IER[RIE]) and received FIFO 0 full enable (IER[RDR0EN]) bits are set, receive interrupt 0 occurs when the received data word is transferred to the receive FIFO 0 and receive FIFO 0 reaches the selected threshold. This results in receive FIFO full 0 (RFF0) flag to set.
PAGE 1531
Chapter 50 Integrated interchip sound (I2S) Note A pull-down resistor is required in the gated clock mode, because the clock port is disabled between transmissions. The Tx data register is loaded with the data to be transmitted. On arrival of the clock, this data is transferred to the transmit shift register which gets transmitted on the STXD output.
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Functional description Gated CLK TX DATA STXD SRXD RX DATA Figure 50-48. Normal mode timing - external gated clock 50.4.1.2 Network mode Network mode creates a time division multiplexed (TDM) network, such as a TDM CODEC network or a network of DSPs. In continuous clock mode, a frame sync occurs at the beginning of each frame. In this mode, the frame is divided into more than one time slot. During each time slot, one data word can be transferred.
PAGE 1533
Chapter 50 Integrated interchip sound (I2S) writing to the TX registers or ignoring the time slot as determined by TMSK register bits. The receiver is treated in the same manner and received data is only transferred to the receive data register/FIFO if the corresponding time slot is enabled through RMSK. By using the TMSK and RMSK registers, software only has to service the I2S during valid time slots. This eliminates any overhead associated with unused time slots.
PAGE 1534
Functional description next time slot. Failing to reload the TX register before the TXSR is finished shifting (empty) causes a transmitter underrun and the TUE error bit is set. In case the FIFO is enabled, the ISR[TFE] flag is set in accordance with the watermark setting and this flag causes the transmitter interrupt to occur. Clearing the TE bit disables the transmitter after completion of transmission of the current frame. Setting the TE bit enables transmission from the next frame.
PAGE 1535
Chapter 50 Integrated interchip sound (I2S) • Read RX and use the data. • Read RX and ignore the data. • Do nothing—the receiver overrun exception occurs at the end of the current time slot. Note For a continuous clock, the optional frame sync output and clock output signals are not affected, even if the transmitter or receiver is disabled. TE and RE do not disable the bit clock or the frame sync generation.
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Functional description CLK FS TX DATA 0x5E REG STXD 0x7B 0xD6 0x5E 0x5E 0xD6 0xD6 0xD6 0x7B 0x55 0x5E 0xD6 0x12 0x34 $7B 0x55 0x5E TDE TUE SRXD RX DATA REG 0xD6 0x12 RDR ROE Note: Processor must write ‘1’ to the corresponding TUE/ROE Interrupt status bit in ISR to clear TUE/ROE Interrupt Figure 50-49. Network mode timing - continuous clock 50.4.1.
PAGE 1537
Chapter 50 Integrated interchip sound (I2S) normal mode), the internal bit clock is enabled onto the appropriate clock port. This allows data to be transferred out in periodic intervals in gated clock mode. With an external clock, the I2S module waits for a clock signal to be received. After the clock begins, valid data is shifted in. Ensure all RCCR[DC] bits are cleared when the module is used in gated mode.
PAGE 1538
Functional description STCK STXD SRXD TCR[TSCKP] = 1, RCR[RSCKP] = 1 Figure 50-53. External gated mode timing - falling edge clocking/rising edge latching Note • The bit clock signals must not have timing glitches. If a single glitch occurs, all ensuing transfers are out of synchronization.
PAGE 1539
Chapter 50 Integrated interchip sound (I2S) Table 50-50. I2S mode selection (continued) CR[I2SMODE] Mode type 10 I2S slave mode 11 Normal mode In normal (non-I2S) mode operation, no register bits are forced to any particular state internally, and the user can program the I2S to work in any operating condition.
PAGE 1540
Functional description • Rx frame sync length set to one-word-long-frame (RCR[RFSL]=0) • Tx shifting w.r.t. bit 0 of TXSR (TCR[TXBIT0] = 1) • Rx shifting w.r.t. bit 0 of RXSR (RCR[RXBIT0] = 1) Set the TCCR[PM, PSR, DIV2, WL, DC] to configure the bit clock and frame sync. The word length is fixed to 32 in I2S master mode and the RCCR[WL] bits determine the number of bits that contain valid data (out of the 32 transmitted/received bits in each channel). 50.4.1.4.
PAGE 1541
Chapter 50 Integrated interchip sound (I2S) 50.4.1.5 AC97 mode In AC97 mode, the I2S transmits a 16-bit tag slot at the start of a frame and the rest of the slots (in that frame) are all 20-bits wide. The same sequence is followed while receiving data. Refer to the AC97 specification for details regarding transmit and receive sequences and data formats.
PAGE 1542
Functional description • Tx frame sync initiated one bit before data is transmitted (TCR[TEFS] = 1) • Rx frame sync initiated one bit before data is received (RCR[REFS] = 1) • Tx shifting w.r.t. bit 0 of TXSR (TCR[TXBIT0] = 1) • Rx shifting w.r.t.
PAGE 1543
Chapter 50 Integrated interchip sound (I2S) While using AC97 in two-channel mode (CR[TCHEN] = 1), it is recommended that the received tag is not stored in the Rx FIFO (ACNT[TIF] = 0). If you need to update the ATAG register and also issue a RD/WR command (in a single frame), it is recommended that the ATAG register is updated prior to issuing a RD/WR command. 50.4.1.5.
PAGE 1544
Functional description • Bit clock — Serially clocks the data bits in and out of the I2S port. This clock is either generated internally or taken from external clock source (through the Tx/Rx clock ports). • Word clock — Counts the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or 24 bits). This clock is generated internally from the bit clock. • Frame clock (frame sync) — Counts the number of words in a frame.
PAGE 1545
Chapter 50 Integrated interchip sound (I2S) 50.4.2.1 I2S clock and frame sync generation Data clock and frame sync signals can be generated internally, or can be obtained from external sources. If internally generated, the I2S clock generator is used to derive bit clock and frame sync signals from the network clock . The I2S clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit rate clock generation.
PAGE 1546
Functional description DC[4:0] Word Clock Frame Sync Frame Rate TFSL TFDIR(1=output) TFSI STFS Tx Frame Sync Out Tx Control TFSI Tx Frame Sync In TFDIR(0=input) Figure 50-57. I2S transmit frame sync generator block diagram 50.4.2.2 DIV2, PSR and PM bits description The bit clock frequency can be calculated from the I2S serial system clock using id-73884. Note You must ensure that the bit-clock frequency must be 5 times the peripheral clock frequency.
PAGE 1547
Chapter 50 Integrated interchip sound (I2S) In the next example, the oversampling clock (network clock) clock is 11.2896 MHz. A 16-bit word network mode with TCCR[DC] = 1, TCCR[PM] = 3, TCCR[PSR] = 0, TCCR[DIV2] = 0, a bit clock rate of 1.4112 MHz is generated. Since the 16-bit word rate is equal to two, the sampling rate (or frame sync rate) would be 1.4112/(2×16) = 44.1 kHz. The following table shows examples of programming the TCCR[PSR] and TCCR[PM] bits to generate various bit clock (STCK) frequencies.
PAGE 1548
Functional description Table 50-51. I2S bit clock and frame rate as a function of PSR, PM, and DIV2 (continued) Bits/ word Words/ frame TCCR MCLK/network clock Bit clock freq (MHz) DIV2 PSR PM WL DC (kHz) Frame rate STCK (kHz) 16 1 11.2896 0 0 7 7 0 705.6 44.1 16 2 11.2896 0 0 3 7 1 1411.2 44.1 16 4 11.2896 0 0 1 7 3 2822.4 44.
PAGE 1549
Chapter 50 Integrated interchip sound (I2S) 50.4.3.1 Supported data alignment formats The I2S supports three data formats to provide flexibility with handling data. These formats dictate how data is written to (and read from) the data registers. Therefore, data can appear in different places in TX0/1 and RX0/1 based on the data format and the number of bits per word.
PAGE 1550
Functional description Table 50-53. Data alignment (continued) 24-bit lsb aligned 24-bit msb aligned 23:0 23:0 In addition, if lsb alignment is selected, the receive data can be zero-extended or signextended. • In zero-extension, all bits above the most significant bit are 0s. This format is useful when data is stored in a pure integer format. • In sign-extension, all bits above the most significant bit are equal to the most significant bit.
PAGE 1551
Chapter 50 Integrated interchip sound (I2S) Table 50-54. I2S receive data interrupts Interrupt RIE ROEn RFFn/RDRn Receive data 0 interrupts (n = 0) Receive data 0 (with exception status) 1 1 1 Receive data 0 (without exception) 1 0 1 Receive data 1 interrupts (n = 1) Receive data 1 (with exception status) 1 1 1 Receive data 1 (without exception) 1 0 1 50.4.
PAGE 1552
Functional description Table 50-55. I2S transmit data interrupts (continued) Interrupt TIE TUEn TFEn/TDEn Transmit data 1 (without exception) 1 0 1 Transmit data 1 interrupts (n = 1) Transmit data 0 (with exception status) 1 1 1 Transmit data 0 (without exception) 1 0 1 50.4.6 Internal frame and clock shutdown During transmit/receive operation, clearing TE/RE stops data transmission/reception when the current frame ends.
PAGE 1553
Chapter 50 Integrated interchip sound (I2S) The following figure is illustrates a transmission case where: • TCR[TXDIR] and TCR[TFDIR] are set • CR[TFRCLKDIS] is set a few frames after clearing CR[TE] • ISR[TRFC] is set at the frame boundary after CR[TE] is cleared. Once software services this interrupt and later sets CR[TFRCLKDIS] bit, the ISR[TRFC] bit is set again at next frame boundary. CLK FS Tx Data CR[TE] CR[TFCLDIS] ISR[TFRC] w1c Figure 50-60.
PAGE 1554
Initialization/application information 2. Set all control bits for configuring the I2S (see the following table ). 3. Enable appropriate interrupts/DMA requests through IER. 4. Set the CR[I2SEN] bit to enable the I2S. 5. In AC97 mode, set the ACNT[AC97EN] bit after programming the ATAG register (if needed, for AC97 Fixed mode). 6. In AC97 fixed mode, do not program the slot request bits without programming the frame valid bits in ATAG register. 7. In gated clock mode, refer to Table 50-3. 8.
PAGE 1555
Chapter 50 Integrated interchip sound (I2S) Table 50-56.
PAGE 1556
Initialization/application information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1556 Freescale Semiconductor, Inc.
PAGE 1557
Chapter 51 General purpose input/output (GPIO) 51.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The general purpose input and output (GPIO) module interfaces to the processor core via a zero wait state interface for maximum pin performance. Accesses of any data size are supported to the GPIO registers.
PAGE 1558
Introduction 51.1.2.1 Run mode In run mode, the GPIO operates normally. 51.1.2.2 Wait mode In wait mode, the GPIO operates normally. 51.1.2.3 Stop mode The GPIO is disabled in stop mode, although the pins retain their state. 51.1.2.4 Debug mode In debug mode, the GPIO operates normally. 51.1.3 GPIO signal descriptions Table 51-1.
PAGE 1559
Chapter 51 General purpose input/output (GPIO) 51.1.3.1 Detailed signal description Table 51-2. GPIO interface-detailed signal descriptions Signal I/O Description PORTA[31:0] I/O General purpose input/output. PORTB[31:0] State meaning Asserted - pin is logic one. PORTC[31:0] Negated - pin is logic zero. PORTD[31:0] Timing Assertion - when output, occurs on rising edge of the system clock. For input, may occur at any time and input may be asserted asynchronously to the system clock.
PAGE 1560
Memory map and register definition GPIO memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page reads zero) 400F_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h 51.2.5/ 1564 400F_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h 51.2.6/ 1564 400F_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h 51.2.1/ 1562 32 W (always reads zero) 0000_0000h 51.2.
PAGE 1561
Chapter 51 General purpose input/output (GPIO) GPIO memory map (continued) Absolute address (hex) Width Access (in bits) Reset value Section/ page 32 W (always reads zero) 0000_0000h 51.2.2/ 1562 32 W (always reads zero) 0000_0000h 51.2.3/ 1563 400F_F0CC Port Toggle Output Register (GPIOD_PTOR) 32 W (always reads zero) 0000_0000h 51.2.4/ 1563 400F_F0D0 Port Data Input Register (GPIOD_PDIR) 32 R 0000_0000h 51.2.
PAGE 1562
Memory map and register definition 51.2.
PAGE 1563
Chapter 51 General purpose input/output (GPIO) 51.2.
PAGE 1564
Memory map and register definition GPIOx_PTOR field descriptions (continued) Field Description 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. 51.2.
PAGE 1565
Chapter 51 General purpose input/output (GPIO) GPIOx_PDDR field descriptions Field 31–0 PDD Description Port data direction 0 1 Pin is configured as general purpose input, if configured for the GPIO function Pin is configured for general purpose output, if configured for the GPIO function 51.3 Functional description 51.3.
PAGE 1566
Functional description K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1566 Freescale Semiconductor, Inc.
PAGE 1567
Chapter 52 Touch sense input (TSI) 52.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement of an electrode having individual programmable detection thresholds and result registers.
PAGE 1568
Overview • Configurable integration of each electrode capacitance measurement from 1 to 4096 times • Programmable electrode oscillator and TSI Reference Oscillator for high sensitivity, small scan time and low power functionality • Only uses one pin per electrode implementation with no external hardware required 52.3 Overview This section presents an overview of the TSI module. The following figure presents the simplified TSI module block diagram.
PAGE 1569
Chapter 52 Touch sense input (TSI) capacitance, while the other according to an internal reference capacitor. The pin capacitance measurement is given by the counted number of periods of the reference oscillator during a configurable number of oscillations of the external electrode oscillator. The electrode oscillator charges and discharges the pin capacitance with a programmable 5-bit binary current source in order to accommodate different sizes of electrode capacitance.
PAGE 1570
Modes of operation electrode scan unit also allows software triggering of the electrode scans. This feature is very useful for initialization of the touch application to detect the initial electrode capacitances. This module generates configurable end-of-scan interrupt to indicate the application that all electrodes were scanned.
PAGE 1571
Chapter 52 Touch sense input (TSI) 52.4.3 TSI low power mode The TSI module enters low power mode if the GENCS[STPE] is set to one and the MCU is programmed into one of the following operational modes: LLS, VLLS1, VLLS2 or VLLS3. In low power mode, only one selectable pin is active, being able to perform capacitance measurements. The scan period is defined by GENCS[LPSCNITV]. Two low power clock sources are available in the TSI low power mode, LPOCLK and VLPOSCCLK, being selected by the GENCS[LPCLKS].
PAGE 1572
TSI signal descriptions 52.5 TSI signal descriptions The TSI module has up to 16 external pins for touch sensing. The table below itemizes all the TSI external pins. Table 52-1. TSI signal descriptions Signal TSI_IN[15:0] Description I/O TSI pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O 52.5.
PAGE 1573
Chapter 52 Touch sense input (TSI) TSI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_5104 Counter Register (TSI0_CNTR3) 32 R 0000_0000h 52.6.5/ 1586 4004_5108 Counter Register (TSI0_CNTR5) 32 R 0000_0000h 52.6.5/ 1586 4004_510C Counter Register (TSI0_CNTR7) 32 R 0000_0000h 52.6.5/ 1586 4004_5110 Counter Register (TSI0_CNTR9) 32 R 0000_0000h 52.6.
PAGE 1574
Memory map and register definition TSI memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_5154 Channel n threshold register (TSI0_THRESHLD13) 32 R/W 0000_0000h 52.6.6/ 1587 4004_5158 Channel n threshold register (TSI0_THRESHLD14) 32 R/W 0000_0000h 52.6.6/ 1587 4004_515C Channel n threshold register (TSI0_THRESHLD15) 32 R/W 0000_0000h 52.6.6/ 1587 52.6.
PAGE 1575
Chapter 52 Touch sense input (TSI) TSIx_GENCS field descriptions (continued) Field Description 0 1 27–24 LPSCNITV 23–19 NSCN LPOCLK VLPOSCCLK TSI Low Power Mode Scan Interval 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 ms scan interval 5 ms scan interval 10 ms scan interval 15 ms scan interval 20 ms scan interval 30 ms scan interval 40 ms scan interval 50 ms scan interval 75 ms scan interval 100 ms scan interval 125 ms scan interval 150 ms scan interval 200 ms sc
PAGE 1576
Memory map and register definition TSIx_GENCS field descriptions (continued) Field Description 11001 11010 11011 11100 11101 11110 11111 26 times per electrode 27 times per electrode 28 times per electrode 29 times per electrode 30 times per electrode 31 times per electrode 32 times per electrode 18–16 PS Electrode oscillator prescaler 15 EOSF End of scan flag 000 001 010 011 100 101 110 111 Electrode oscillator frequency divided by 1 Electrode oscillator frequency divided by 2 Electrode oscillator
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Chapter 52 Touch sense input (TSI) TSIx_GENCS field descriptions (continued) Field Description 0 1 5 ERIE Disable Enable TSI error interrupt Enable Caused by a short or overrun error. 0 1 4 ESOR Error interrupt disabled Error interrupt enabled End-of-scan or out-of-range interrupt select 0 1 Out-of-range interrupt selected End-of-scan interrupt selected 3 Reserved Reserved 2 Reserved Reserved This field is reserved. This field is reserved.
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Memory map and register definition TSIx_SCANC field descriptions Field 31–27 REFCHRG 26–24 CAPTRM 23–19 EXTCHRG Description Reference oscillator charge current select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 µA charge current 2 µA charge current 3 µA charge current 4 µA charge current 5 µA charge current 6 µA charge current 7 µA charge current 8 µA cha
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Chapter 52 Touch sense input (TSI) TSIx_SCANC field descriptions (continued) Field Description 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 18–16 DELVOL 15–8 SMOD 7–6 Reserved 2 µA charge current 3 µA charge current 4 µA charge current 5 µA charge current 6 µA charge current 7 µA charge current 8 µA charge current 9 µA charge current 10 µA charge current 11 µA ch
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Memory map and register definition TSIx_SCANC field descriptions (continued) Field Description 5 AMCLKDIV Active mode clock divider 4–3 AMCLKS Active mode clock source 2–0 AMPSC Active mode prescaler 0 1 00 01 10 11 Divider set to 1 Divider set to 2048 Bus Clock MCGIRCLK OSCERCLK Not valid 000 001 010 011 100 101 110 111 Input clock source divided by 1 Input clock source divided by 2 Input clock source divided by 4 Input clock source divided by 8 Input clock source divided by 16 Input clock so
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Chapter 52 Touch sense input (TSI) TSIx_PEN field descriptions (continued) Field Description Selects which input is active in low-power mode.
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Memory map and register definition TSIx_PEN field descriptions (continued) Field Description 8 PEN8 TSI pin 8 enable 7 PEN7 TSI pin 7 enable 6 PEN6 TSI pin 6 enable 5 PEN5 TSI pin 5 enable 4 PEN4 TSI pin 4 enable 3 PEN3 TSI pin 3 enable 2 PEN2 TSI pin 2 enable 1 PEN1 TSI pin 1 enable 0 PEN0 TSI pin 0 enable 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The corresponding pin is not used by TSI The corresponding pin is used by TSI The corresponding pin is not used by TSI The corresponding
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Chapter 52 Touch sense input (TSI) 52.6.
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Memory map and register definition TSIx_STATUS field descriptions (continued) Field Description This bit indicates when the corresponding electrode is shorted to VDD or VSS. If the GENCS[ERIE] bit is set, an error interrupt is generated. Write a one to clear this bit.
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Chapter 52 Touch sense input (TSI) TSIx_STATUS field descriptions (continued) Field Description This bit indicates when the corresponding electrode is out of range. If the GENCS[TSIIE] bit is set and the GENCS[ESOR] bit is cleared, an out-of-range interrupt is generated. Write a one to clear this bit.
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Memory map and register definition TSIx_STATUS field descriptions (continued) Field Description This bit indicates when the corresponding electrode is out of range. If the GENCS[TSIIE] bit is set and the GENCS[ESOR] bit is cleared, an out-of-range interrupt is generated. Write a one to clear this bit. 1 ORNGF1 Touch Sensing Electrode Out-of-Range Flag 1 0 ORNGF0 Touch Sensing Electrode Out-of-Range Flag 0 This bit indicates when the corresponding electrode is out of range.
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Chapter 52 Touch sense input (TSI) 52.6.6 Channel n threshold register (TSIx_THRESHLD) All THRESHLD bits can be read at any time, but must not be written while GENCS[SCNIP] is set.
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Functional descriptions Electrode charge current (EXTCHRG) Delta Voltage (DELVOL) Figure 52-64. TSI electrode oscillator circuit The current source applied to the pad capacitance is 5-bit binary controlled by the SCANC[EXTCHRG]. The hysteresis delta voltage is also configurable and is 3-bit binary controlled by the SCANC[DELVOL]. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current.
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Chapter 52 Touch sense input (TSI) So by this equation, for example, an electrode with Celec= 20 pF, with a current source of I = 16 µA and ΔV = 600 mV will have the following oscillation frequency: Felec 16 µA 2 * 20pF * 600mV 0.67MHz Figure 52-67. Equation 2: TSI electrode oscillator frequency The current source and hysteresis delta voltage are used to accommodate the TSI electrode oscillator frequency with different electrode capacitance sizes. 52.7.1.
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Functional descriptions Tcap_samp 2*2*16*20pF*600mV 48µs 16µA 52.7.1.3 TSI reference oscillator The TSI reference oscillator has the same topology of the TSI electrode oscillator. The TSI reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor which can be programmable. The SCANC[CAPTRM] defines the internal reference capacitor trimming value *.
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Chapter 52 Touch sense input (TSI) TSICHnCNT Iref * PS *NSCN * Celec Cref * Iref Figure 52-70. Equation 5: Capacitance result value In the example where Fref_osc = 10.0MHz and Tcap_samp = 48 µs, TSICHnCNT = 480 52.7.3 Electrode scan unit This section describes the functionality of the electrode scan unit. It is responsible for triggering the start of the active electrode scan. The touch sense input module needs to periodically scan all active electrodes to determine if a touch event has occurred.
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Functional descriptions 52.7.3.2 Scan trigger The scan trigger can be set to periodical scan or software trigger. The bit GENCS[STM] determines the TSI scan trigger mode. If STM = 1 the trigger mode is selected as continuous. If STM = 0, the software trigger mode is selected. In periodic mode the scan trigger is generated automatically by the electrode scan unit. NOTE It takes some time (less than 40 µs) for TSI oscillators to be stable in software trigger mode and periodical scan mode.
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Chapter 52 Touch sense input (TSI) First Active Electrode Scan States ... ... ... Result Counter ... Last Scan 1st Scan 1st Scan Last Active Electrode Second Active Electrode Count from 0 to result Count from 0 to result Last Scan 1st Scan Last Scan ... ... ... ... ... ... ... Count from 0 to result End-of-Scan Signal Figure 52-71. Scan sequence 52.7.3.4.2 Low power mode scan In low power periodic scan, the scan period is define by the 4-bit binary GENCS[LPSCNITV].
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Functional descriptions It is worthy to note that, since all the possible flags are asserted upon the end of scan event, in TSI interrupt service routine, the end-of-scan flag will be always set until the software clears it. 52.7.3.4.4 Over-run interrupt If an electrode scan is in progress and there is a scan trigger, the electrode scan unit generates an over-run error by asserting the GENCS[OVRF]. If the TSI error interrupt is active by setting the GENCS[ERIE] bit a interrupt request is asserted.
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Chapter 52 Touch sense input (TSI) When GENCS[OUTRGF] flag is asserted, it is requested the software to poll which specific electrode is out of range by reading the status from STATUS register, clearing the corresponding electrodes flags will also clear the out-of-range flag in GENCS[OUTRGF]. 52.7.4.2 Error interrupt The GENCS[EXTERF] is set in the case the capacitance result registers, TSICHnCNT, of a TSI pin is either 0 or 0xFFFF, the two possible extreme values.
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Application information K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1596 Freescale Semiconductor, Inc.
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Chapter 53 JTAG Controller (JTAGC) 53.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. 53.1.
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Introduction Power-on reset Test Access Port (TAP) Controller TMS TCK 1-bit Bypass Register 32-bit Device Identification Register TDI TDO Boundary Scan Register TAP Instruction Decoder TAP Instruction Register Figure 53-1. JTAG (IEEE 1149.1) block diagram 53.1.2 Features The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features: • IEEE 1149.
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Chapter 53 JTAG Controller (JTAGC) 53.1.3.1 Reset The JTAGC block is placed in reset when either power-on reset is asserted, or the TMS input is held high for enough consecutive rising edges of TCK to sequence the TAP controller state machine into the Test-Logic-Reset state. Holding TMS high for five consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state regardless of the current TAP controller state. Asserting power-on reset results in asynchronous entry into the reset state.
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External signal description 53.2 External signal description The JTAGC consists of a set of signals that connect to off chip development tools and allow access to test support functions. The JTAGC signals are outlined in the following table and described in the following sections. Table 53-1. JTAG signal properties Name I/O Function Reset State Pull TCK Input Test Clock — Down TDI Input Test Data In — Up TDO Output Test Data Out High Z1 — TMS Input Test Mode Select — Up 1.
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Chapter 53 JTAG Controller (JTAGC) 53.3 Register description This section provides a detailed description of the JTAGC block registers accessible through the TAP interface, including data registers and the instruction register. Individual bit-level descriptions and reset states of each register are included. These registers are not memory-mapped and can only be accessed through the TAP. 53.3.1 Instruction register The JTAGC block uses a 4-bit instruction register as shown in the following figure.
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Register description 53.3.3 Device identification register The device identification (JTAG ID) register, shown in the following figure, allows the revision number, part number, manufacturer, and design center responsible for the design of the part to be determined through the TAP. The device identification register is selected for serial data transfer between TDI and TDO when the IDCODE instruction is active.
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Chapter 53 JTAG Controller (JTAGC) scan register cell, as described in the IEEE 1149.1-2001 standard and discussed in Boundary scan. The size of the boundary scan register and bit ordering is devicedependent and can be found in the device BSDL file. 53.4 Functional description This section explains the JTAGC functional description. 53.4.
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Functional description TEST LOGIC RESET 1 0 1 1 1 SELECT-DR-SCAN RUN-TEST/IDLE SELECT-IR-SCAN 0 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-IR SHIFT-DR 0 0 1 1 1 1 EXIT1-IR EXIT1-DR 0 0 PAUSE-DR PAUSE-IR 0 0 1 0 EXIT2-DR 1 0 EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 53-4. IEEE 1149.1-2001 TAP controller finite state machine 53.4.3.
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Chapter 53 JTAG Controller (JTAGC) 53.4.3.2 Selecting an IEEE 1149.1-2001 register Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC block instructions while the JTAGC is enabled. Instructions are shifted in via the Select-IR-Scan path and loaded in the Update-IR state. At this point, all data register access is performed via the Select-DR-Scan path.
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Functional description Table 53-3. 4-bit JTAG instructions (continued) Instruction Code[3:0] Instruction Summary ARM JTAG-DP Reserved 1011 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information. CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset ARM JTAG-DP Reserved 1110 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information.
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Chapter 53 JTAG Controller (JTAGC) of the boundary scan register cells on the falling edge of TCK in the Update-DR state. The data is applied to the external output pins by the EXTEST or CLAMP instruction. System operation is not affected. 53.4.4.4 SAMPLE instruction The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins.
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Initialization/Application information single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system reset for the MCU to force a predictable internal state. 53.4.4.8 BYPASS instruction BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no test operation of the MCU is required.
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Appendix A Release Notes for Revision 6 A.1 General changes throughout document • No substantial content changes A.2 About This Document chapter changes • No substantial content changes A.3 Introduction chapter changes • Updated 'Kinetis MCU portfolio' diagram for K6x family. A.4 Chip Configuration chapter changes • • • • • Clarified 'PDB Module Interconnections' section. In 'UART interrupts' section, updated LON and ISO7816 interrupt sources. Clarified 'I2S/SAI clock generation' section.
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Memory Map chapter changes A.5 Memory Map chapter changes • Added Alternate non-volatile IRC user trim description topic. A.6 Clock Distribution chapter changes • Added 'SAI clock generation' diagram. • Updated Clock Diagram for standard XTAL, EXTAL, and MCG clock names. • In Device Clock Summary table, updated bus clock, external reference clock, USB FS clock, and TRACE clock. • Updated Clocking diagram for IRC clock and updated MCGFFCLK definition. • Added note to Debug trace clock section.
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Appendix A Release Notes for Revision 6 A.11 Signal Multiplexing and Signal Descriptions chapter changes • Updated pinout diagrams and tables • In 'Port control and interrupt module features' section, updated digital filter clock cycles from 1 to 32. • Updated CMPx_IN signals to 5:0. • In 'System Signal Descriptions' table, modified RESET_b pin to I/O. • For the "Signal Multiplexing and Pin Assignments" table, added the LLWU inputs to the appropriate pin names. A.
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Crossbar switch chapter changes A.18 Crossbar switch chapter changes • No substantial content changes A.19 MPU changes • No substantial content changes A.20 AIPS-Lite changes • No substantial content changes A.21 DMAMUX changes • No substantial content changes A.22 DMA changes • No substantial content changes A.23 EWM changes • No substantial content changes A.
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Appendix A Release Notes for Revision 6 A.26 OSC changes • No substantial content changes A.27 RTC Oscillator changes • No substantial content changes A.28 FMC changes • Terminology update: changed "Directory" to "Tag" in the names of tag cache registers. A.
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CRC changes A.32 CRC changes No substantial content changes A.33 ADC changes • Removed CLPD from generating gain calibration values procedure. • Updated Pseudo-code example section for CFG1 and SC2 register bits. • Removed band gap voltages, BGH and BGL. A.34 CMP changes • Updated CMPx_CR1[PMODE] field description. A.35 DAC changes • Updated DACx_C0[LPEN] field description. A.36 VREF changes • No substantial content changes A.37 PDB changes Added Debug mode and updated PDBEN encodings. A.
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Appendix A Release Notes for Revision 6 A.39 PIT changes • No substantial content changes A.40 LPTMR changes • Added note in LPTMR clocking section. A.41 CMT changes • No substantial content changes A.42 RTC changes Updated RTC_CR[14] bit field access. Updated Time Alarm section with IER[TAIE]. A.43 USB changes • No substantial content changes A.44 USBDCD changes • No substantial content changes A.45 USB VREG changes • No substantial content changes A.
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DSPI chapter changes A.47 DSPI chapter changes • In 'Transmit FIFO Fill Interrupt or DMA Request' section, added note on using TFFF flag. • • • • • • Added links to corresponding functional description in the Delay fields in CTAR register. Renamed DSICR to DSICR0. Updated EOQ interrupt request description. Added SPITCF and DSITCF interrupt request descriptions and updated corresponding bit fields in SR register. Updated DIS_TXF and DIS_RXF bit field descriptions in MCR register.
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A.54 JTAG Controller changes • No substantial content changes K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
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K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 1618 Freescale Semiconductor, Inc.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.