Information

Section Number Title Page
10.2 Signal Multiplexing Integration....................................................................................................................................219
10.2.1 Port control and interrupt module features..................................................................................................220
10.2.2 Clock gating.................................................................................................................................................220
10.2.3 Signal multiplexing constraints....................................................................................................................220
10.3 Pinout............................................................................................................................................................................220
10.3.1 K20 Signal Multiplexing and Pin Assignments...........................................................................................221
10.3.2 K20 Pinouts..................................................................................................................................................226
10.4 Module Signal Description Tables................................................................................................................................228
10.4.1 Core Modules...............................................................................................................................................228
10.4.2 System Modules...........................................................................................................................................229
10.4.3 Clock Modules.............................................................................................................................................230
10.4.4 Memories and Memory Interfaces...............................................................................................................230
10.4.5 Analog..........................................................................................................................................................231
10.4.6 Communication Interfaces...........................................................................................................................233
10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................236
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................239
11.1.1 Overview......................................................................................................................................................239
11.1.2 Features........................................................................................................................................................239
11.1.3 Modes of operation......................................................................................................................................240
11.2 External signal description............................................................................................................................................241
11.3 Detailed signal descriptions..........................................................................................................................................241
11.4 Memory map and register definition.............................................................................................................................241
11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................248
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................250
11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................251
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................251
11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................252
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
10 Freescale Semiconductor, Inc.