Information

SRAM upper
Transfers
SRAM controller
Cortex-M4
core
MPU
Crossbar
switch
SRAM lower
MPU
Figure 3-23. SRAM configuration
Table 3-37. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking Clock Distribution
Transfers SRAM controller SRAM controller
ARM Cortex-M4 core ARM Cortex-M4 core
Memory protection unit Memory protection unit
3.5.3.1 SRAM sizes
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of
SRAM for the devices covered in this document is shown in the following table.
Device SRAM (KB)
MK20DX256ZVLK10 64
MK20DN512ZVLK10 128
MK20DX256ZVMB10 64
MK20DN512ZVMB10 128
3.5.3.2 SRAM Arrays
The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and
SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Memories and Memory Interfaces
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
100 Freescale Semiconductor, Inc.