Information

Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1]
This is illustrated in the following figure.
SRAM_U
0x2000_0000
SRAM size / 2
SRAM_L
0x1FFF_FFFF
SRAM size / 2
0x2000_0000 – SRAM_size/2
0x2000_0000 + SRAM_size/2 - 1
Figure 3-24. SRAM blocks memory map
For example, for a device containing 64 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_7FFF
3.5.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode.
In VLLS2 the 4 KB region of SRAM_U from 0x2000_0000 is powered.
In VLLS1 no SRAM is retained. However, the 32-byte register file is available in
VLLS1.
3.5.3.4 SRAM accesses
The SRAM is split into two logical arrays that are 32-bits wide.
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
port.
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the
backdoor port.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 101