Information

40.6.5 CMT Output Control Register (CMT_OC)
This register is used to control the IRO signal of the CMT module.
Address: CMT_OC is 4006_2000h base + 4h offset = 4006_2004h
Bit 7 6 5 4 3 2 1 0
Read
IROL CMTPOL IROPEN
0
Write
Reset
0 0 0 0 0 0 0 0
CMT_OC field descriptions
Field Description
7
IROL
IRO Latch Control
Reading IROL reads the state of the IRO latch. Writing to IROL changes the state of the CMT_IRO signal
when MSC[MCGEN] bit is cleared and the IROPEN bit is set.
6
CMTPOL
CMT Output Polarity
The CMTPOL bit controls the polarity of the CMT_IRO signal of the CMT.
0 CMT_IRO signal is active low
1
CMT_IRO signal is active high
5
IROPEN
IRO Pin Enable
The IROPEN bit is used to enable and disable the CMT_IRO signal. When CMT_IRO signal is enabled, it
is an output that drives out either the CMT transmitter output or the state of the IROL bit depending on
whether MSC[MCGEN] bit is set or not. Also, the state of the output is either inverted or not depending on
the state of the CMTPOL bit. When CMT_IRO signal is disabled, it is in a high impedance state so as not
to draw any current. This signal is disabled during reset.
0 CMT_IRO signal disabled
1
CMT_IRO signal enabled as output
4–0
Reserved
This read-only field is reserved and always has the value zero.
Chapter 40 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1013