Information

41.2.9 RTC Write Access Register (RTC_WAR)
Address: RTC_WAR is 4003_D000h base + 800h offset = 4003_D800h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IERW
LRW
SRW
CRW
TCRW
TARW
TPRW TSRW
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_WAR field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
IERW
Interrupt Enable Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the interupt enable register are ignored.
1 Writes to the interrupt enable register complete as normal.
6
LRW
Lock Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the lock register are ignored.
1 Writes to the lock register complete as normal.
5
SRW
Status Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the status register are ignored.
1 Writes to the status register complete as normal.
4
CRW
Control Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the control register are ignored.
1 Writes to the control register complete as normal.
3
TCRW
Time Compensation Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the time compensation register are ignored.
1 Writes to the time compensation register complete as normal.
2
TARW
Time Alarm Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the time alarm register are ignored.
1 Writes to the time alarm register complete as normal.
Table continues on the next page...
Chapter 41 Real Time Clock (RTC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1039