Information

Register file
Peripheral
bridge 0
Register
access
Figure 3-27. System Register file configuration
Table 3-39. Reference links to related information
Topic Related module Reference
Full description Register file Register file
System memory map System memory map
Clocking Clock distribution
Power management Power management
3.5.5.1 System Register file
This device includes a 32-byte register file that is powered in all power modes.
Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.
3.5.6 VBAT Register File Configuration
This section summarizes how the module has been configured in the chip.
Memories and Memory Interfaces
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
104 Freescale Semiconductor, Inc.