Information

Table 42-5. USB Responses to DMA Overrun Errors (continued)
Errors due to Memory Latency Errors due to Oversized Packets
—
The data written to memory is clipped to the MaxPacket size
so as not to corrupt system memory.
The DMA_ERR bit is set in the ERR_STAT register for host
and device modes of operation. Depending on the values of
the INT_ENB and ERR_ENB register, the core may assert an
interrupt to notify the processor of the DMA error.
Asserts the DMA_ERR bit of the ERR_STAT register (which
could trigger an interrupt) and a TOK_DNE interrupt fires.
(Note: The TOK_PID field of the BDT is not 1111 because
the DMA_ERR is not due to latency).
• For host mode, the TOK_DNE interrupt fires and the
TOK_PID field of the BDT is 1111 to indicate the DMA
latency error. Host mode software can decide to retry
or move to next scheduled item.
• In device mode, the BDT is not written back nor is the
TOK_DNE interrupt triggered because it is assumed
that a second attempt is queued and will succeed in the
future.
The packet length field written back to the BDT is the
MaxPacket value that represents the length of the clipped
data actually written to memory.
From here, the software can decide an appropriate course of action for future transactions such as stalling the endpoint,
canceling the transfer, disabling the endpoint, etc.
42.4 Memory Map/Register Definitions
This section provides the memory map and detailed descriptions of all USB interface
registers.
USB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_2000 Peripheral ID Register (USB0_PERID) 8 R 04h
42.4.1/
1059
4007_2004 Peripheral ID Complement Register (USB0_IDCOMP) 8 R FBh
42.4.2/
1060
4007_2008 Peripheral Revision Register (USB0_REV) 8 R 33h
42.4.3/
1060
4007_200C Peripheral Additional Info Register (USB0_ADDINFO) 8 R 01h
42.4.4/
1061
4007_2010 OTG Interrupt Status Register (USB0_OTGISTAT) 8 R/W 00h
42.4.5/
1061
4007_2014 OTG Interrupt Control Register (USB0_OTGICR) 8 R/W 00h
42.4.6/
1062
4007_2018 OTG Status Register (USB0_OTGSTAT) 8 R/W 00h
42.4.7/
1063
Table continues on the next page...
Chapter 42 Universal Serial Bus OTG Controller (USBOTG)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1057