Information

USBx_OTGISTAT field descriptions (continued)
Field Description
5
LINE_STATE_
CHG
This bit is set when the USB line state changes. The interrupt associated with this bit can be used to
detect Reset, Resume, Connect, and Data Line Pulse signals.
4
Reserved
This read-only field is reserved and always has the value zero.
3
SESSVLDCHG
This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid.
2
B_SESS_CHG
This bit is set when a change in VBUS is detected on a B device.
1
Reserved
This read-only field is reserved and always has the value zero.
0
AVBUSCHG
This bit is set when a change in VBUS is detected on an A device.
42.4.6 OTG Interrupt Control Register (USBx_OTGICR)
The OTG Interrupt Control Register enables the corresponding interrupt status bits
defined in the OTG Interrupt Status Register.
Addresses: USB0_OTGICR is 4007_2000h base + 14h offset = 4007_2014h
Bit 7 6 5 4 3 2 1 0
Read
IDEN
ONEMSECEN LINESTATEEN
0
SESSVLDEN
BSESSEN
0
AVBUSEN
Write
Reset
0 0 0 0 0 0 0 0
USBx_OTGICR field descriptions
Field Description
7
IDEN
ID interrupt enable
0 The ID interrupt is disabled
1 The ID interrupt is enabled
6
ONEMSECEN
1 millisecond interrupt enable
0 The 1msec timer interrupt is disabled.
1 The 1msec timer interrupt is enabled.
5
LINESTATEEN
Line State change interrupt enable
0 The LINE_STAT_CHG interrupt is disabled.
1 The LINE_STAT_CHG interrupt is enabled
4
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory Map/Register Definitions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1062 Freescale Semiconductor, Inc.