Information

Signal multiplexing
Module signals
Register
access
FlexBus
Transfers
Memory protection
unit
Peripheral
bridge 0
Crossbar switch
Figure 3-30. FlexBus configuration
Table 3-42. Reference links to related information
Topic Related module Reference
Full description FlexBus FlexBus
System memory map System memory map
Clocking Clock distribution
Power management Power management
Transfers Memory protection unit
(MPU)
Memory protection unit (MPU)
Signal multiplexing Port control Signal multiplexing
3.5.8.1 FlexBus clocking
The system provides a dedicated clock source to the FlexBus module's external
FB_CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See
Clock Distribution for more details.
3.5.8.2 FlexBus signal multiplexing
The multiplexing of the FlexBus address and data signals is controlled by the port control
module. However, the multiplexing of some of the FlexBus control signals are controlled
by the port control and FlexBus modules. The port control module registers control
whether the FlexBus or another module signals are available on the external pin, while
the FlexBus's CSPMCR register configures which FlexBus signals are available from the
module. The control signals are grouped as illustrated:
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 107