Information

USBDCD memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_5008 Status Register (USBDCD_STATUS) 32 R 0000_0000h
43.4.3/
1096
4003_5010 TIMER0 Register (USBDCD_TIMER0) 32 R/W 0010_0000h
43.4.4/
1098
4003_5014 USBDCD_TIMER1 32 R/W 000A_0028h
43.4.5/
1099
4003_5018 USBDCD_TIMER2 32 R/W 0028_0001h
43.4.6/
1099
43.4.1 Control Register (USBDCD_CONTROL)
Contains the control and interrupt bit fields.
Address: USBDCD_CONTROL is 4003_5000h base + 0h offset = 4003_5000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0
0
0
IE
W
SR
START
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
IF 0 0
W
IACK
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
USBDCD_CONTROL field descriptions
Field Description
31–26
Reserved
This read-only field is reserved and always has the value zero.
25
SR
Software Reset
Determines whether a software reset is performed.
0 Do not perform a software reset.
1 Perform a software reset.
24
START
Start Change Detection Sequence
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1094 Freescale Semiconductor, Inc.