Information

• Sets the CONTROL[IF] bit.
• Generates an interrupt if enabled (the CONTROL[IE] bit is set).
At this point, control has been passed to system software via the interrupt. The rest of the
sequence (detecting the type of charging port) is not applicable, so software should:
1. Read the STATUS register.
2. Set the CONTROL[IACK] bit to acknowledge the interrupt.
3. Set the CONTROL[SR] bit to issue a software reset to the module.
4. Disable the module.
5. Communicate the appropriate charge rate to the external battery charger IC; see
Table 43-13.
43.5.1.4.2 Charging Port
As part of the charger detection handshake with any type of USB host, the module waits
until the T
VDPSRC_CON
interval has elapsed before doing the following:
• Updates the STATUS register to reflect that a charging port has been detected with
SEQ_RES = 10. (See Table 43-18 for field values.)
• Sets the CONTROL[IF] bit.
• Generates an interrupt if enabled (the CONTROL[IE] bit is set).
At this point, control has passed to system software via the interrupt. Software should:
1. Read the STATUS register.
2. Set the CONTROL[IACK] bit to acknowledge the interrupt.
3. Issue a command to the USB controller to pullup the USB D+ line.
4. Wait for the module to complete the final phase of the sequence. See Charger Type
Detection.
43.5.1.4.3 Error in Charging Port Detection
For this error condition, the module does the following:
Chapter 43 USB Device Charger Detection Module (USBDCD)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1107