Information

3.7.1.6 ADC Hardware Interleaved Channels
The AD8 and AD9 channels on ADCx are interleaved in hardware using the following
configuration.
ADC0
AD8
AD9
ADC1
AD8
AD9
ADC0_SE8/ADC1_SE8
ADC0_SE9/ADC1_SE9
Figure 3-35. ADC hardware interleaved channels integration
3.7.1.7 ADC and PGA Reference Options
The ADC supports the following references:
• VREFH/VREFL - connected as the primary reference option
• 1.2 V VREF_OUT - connected as the V
ALT
reference option
ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to
REFSEL description in ADC chapter for more details.
The only reference option for the PGA is the 1.2 V VREF_OUT source. The VREF_OUT
signal can either be driven by an external voltage source via the VREF_OUT pin or from
the output of the VREF module. Ensure that the VREF module is disabled when an
external voltage source is used instead. For PGA maximum differential input signal
swing range, refer to the device data sheet for 16-bit ADC with PGA characteristics.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 115