Information
Section Number Title Page
12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................286
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................287
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................288
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................289
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................290
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................290
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................291
12.3 Functional description...................................................................................................................................................291
Chapter 13
Mode Controller
13.1 Introduction...................................................................................................................................................................293
13.1.1 Features........................................................................................................................................................293
13.1.2 Modes of Operation.....................................................................................................................................293
13.1.3 MCU Reset...................................................................................................................................................304
13.2 Mode Control Memory Map/Register Definition.........................................................................................................307
13.2.1 System Reset Status Register High (MC_SRSH)........................................................................................308
13.2.2 System Reset Status Register Low (MC_SRSL).........................................................................................309
13.2.3 Power Mode Protection Register (MC_PMPROT).....................................................................................310
13.2.4 Power Mode Control Register (MC_PMCTRL)..........................................................................................312
Chapter 14
Power Management Controller
14.1 Introduction...................................................................................................................................................................315
14.2 Features.........................................................................................................................................................................315
14.3 Low-Voltage Detect (LVD) System.............................................................................................................................315
14.3.1 LVD Reset Operation...................................................................................................................................316
14.3.2 LVD Interrupt Operation.............................................................................................................................316
14.3.3 Low-Voltage Warning (LVW) Interrupt Operation.....................................................................................316
14.4 PMC Memory Map/Register Definition.......................................................................................................................317
14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................317
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
12 Freescale Semiconductor, Inc.