Information

• If Rx FIFO was enabled, the ID filter table must be initialized
• Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up
interrupt
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
Initialization/Application Information
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1202 Freescale Semiconductor, Inc.