Information

46.2.2 PCS1 - PCS3 — Peripheral Chip Selects 1 - 3
PCS1 - PCS3 are Peripheral Chip Select output signals in master mode.
In slave mode, these signals are unused.
46.2.3 PCS4 — Peripheral Chip Select 4
In master mode, PCS4 is a Peripheral Chip Select output signal.
In slave mode, this signal is unused.
46.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip
Select Strobe
PCS5 is a Peripheral Chip Select output signal. When the DSPI is in master mode and the
MCR[PCSSE] bit is cleared, this signal selects which slave device the current transfer is
intended for.
When the DSPI is in master mode and the MCR[PCSSE] bit is set, the
PCSS signal acts
as a strobe to an external peripheral chip select demultiplexer, which decodes the PCS0 -
PCS4 signals, preventing glitches on the demultiplexer outputs.
This signal is not used in slave mode.
46.2.5 SIN — Serial Input
SIN is a serial data input signal.
46.2.6 SOUT — Serial Output
SOUT is a serial data output signal.
46.2.7 SCK — Serial Clock
SCK is a serial communication clock signal. In master mode, the DSPI generates the
SCK. In slave mode, SCK is an input from an external bus master.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1209