Information

SPI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C084 DSPI Receive FIFO Registers (SPI0_RXFR2) 32 R 0000_0000h
46.3.11/
1230
4002_C088 DSPI Receive FIFO Registers (SPI0_RXFR3) 32 R 0000_0000h
46.3.11/
1230
4002_D000 DSPI Module Configuration Register (SPI1_MCR) 32 R/W 0000_4001h
46.3.1/
1212
4002_D008 DSPI Transfer Count Register (SPI1_TCR) 32 R/W 0000_0000h
46.3.2/
1215
4002_D00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI1_CTAR0)
32 R/W 7800_0000h
46.3.3/
1215
4002_D00C
DSPI Clock and Transfer Attributes Register (In Slave
Mode) (SPI1_CTAR0_SLAVE)
32 R/W 7800_0000h
46.3.4/
1220
4002_D010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI1_CTAR1)
32 R/W 7800_0000h
46.3.3/
1215
4002_D02C DSPI Status Register (SPI1_SR) 32 R/W See section
46.3.5/
1221
4002_D030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI1_RSER)
32 R/W 0000_0000h
46.3.6/
1224
4002_D034
DSPI PUSH TX FIFO Register In Master Mode
(SPI1_PUSHR)
32 R/W 0000_0000h
46.3.7/
1226
4002_D034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI1_PUSHR_SLAVE)
32 R/W 0000_0000h
46.3.8/
1227
4002_D038 DSPI POP RX FIFO Register (SPI1_POPR) 32 R 0000_0000h
46.3.9/
1228
4002_D03C DSPI Transmit FIFO Registers (SPI1_TXFR0) 32 R 0000_0000h
46.3.10/
1229
4002_D040 DSPI Transmit FIFO Registers (SPI1_TXFR1) 32 R 0000_0000h
46.3.10/
1229
4002_D044 DSPI Transmit FIFO Registers (SPI1_TXFR2) 32 R 0000_0000h
46.3.10/
1229
4002_D048 DSPI Transmit FIFO Registers (SPI1_TXFR3) 32 R 0000_0000h
46.3.10/
1229
4002_D07C DSPI Receive FIFO Registers (SPI1_RXFR0) 32 R 0000_0000h
46.3.11/
1230
4002_D080 DSPI Receive FIFO Registers (SPI1_RXFR1) 32 R 0000_0000h
46.3.11/
1230
4002_D084 DSPI Receive FIFO Registers (SPI1_RXFR2) 32 R 0000_0000h
46.3.11/
1230
4002_D088 DSPI Receive FIFO Registers (SPI1_RXFR3) 32 R 0000_0000h
46.3.11/
1230
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1211