Information

Addresses: SPI0_CTAR0 is 4002_C000h base + Ch offset = 4002_C00Ch
SPI0_CTAR1 is 4002_C000h base + 10h offset = 4002_C010h
SPI1_CTAR0 is 4002_D000h base + Ch offset = 4002_D00Ch
SPI1_CTAR1 is 4002_D000h base + 10h offset = 4002_D010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DBR FMSZ
CPOL
CPHA
LSBFE
PCSSCK PASC PDT PBR
W
Reset
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CSSCK ASC DT BR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_CTARn field descriptions
Field Description
31
DBR
Double Baud Rate
Doubles the effective baud rate of the Serial Communications Clock (SCK). This field is used only in
master mode. It effectively halves the Baud Rate division ratio, supporting faster frequencies, and odd
division ratios for the Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
Serial Communications Clock (SCK) depends on the value in the Baud Rate Prescaler and the Clock
Phase bit as listed in the following table. See the BR field description for details on how to compute the
baud rate.
Table 46-32. DSPI SCK Duty Cycle
DBR CPHA PBR SCK Duty Cycle
0 any any 50/50
1 0 00 50/50
1 0 01 33/66
1 0 10 40/60
1 0 11 43/57
1 1 00 50/50
1 1 01 66/33
1 1 10 60/40
1 1 11 57/43
0 The baud rate is computed normally with a 50/50 duty cycle.
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
30–27
FMSZ
Frame Size
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1216 Freescale Semiconductor, Inc.