Information

SPIx_CTARn field descriptions (continued)
Field Description
Table 46-34. DSPI Baud Rate Scaler (continued)
CTARn[BR] Baud Rate Scaler Value
1001 512
1010 1024
1011 2048
1100 4096
1101 8192
1110 16384
1111 32768
46.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode)
(SPIx_CTAR_SLAVE)
When the DSPI is configured as an SPI bus slave, the CTAR0 register is used.
Addresses: SPI0_CTAR0_SLAVE is 4002_C000h base + Ch offset = 4002_C00Ch
SPI1_CTAR0_SLAVE is 4002_D000h base + Ch offset = 4002_D00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FMSZ
CPOL
CPHA
0 0
W
Reset
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_CTARn_SLAVE field descriptions
Field Description
31–27
FMSZ
Frame Size
The number of bits transferred per frame is equal to the FMSZ field value plus 1. The minimum valid
FMSZ field value is 3.
26
CPOL
Clock Polarity
Selects the inactive state of the Serial Communications Clock (SCK).
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
25
CPHA
Clock Phase
Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is
used in both master and slave mode. For successful communication between serial devices, the devices
must have identical clock phase settings. In Continuous SCK mode, the bit value is ignored and the
transfers are done as the CPHA bit is set to 1.
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1220 Freescale Semiconductor, Inc.