Information

SPIx_PUSHR field descriptions (continued)
Field Description
27
EOQ
End Of Queue
Host software uses this bit to signal to the DSPI that the current SPI transfer is the last in a queue. At the
end of the transfer, the EOQF bit in the SR is set.
0 The SPI data is not the last data to transfer.
1 The SPI data is the last data to transfer.
26
CTCNT
Clear Transfer Counter.
Clears the SPI_TCNT field in the TCR register. The SPI_TCNT field is cleared before the DSPI starts
transmitting the current SPI frame.
0 Do not clear the TCR[SPI_TCNT] field.
1 Clear the TCR[SPI_TCNT] field.
25–24
Reserved
This read-only field is reserved and always has the value zero.
23–22
Reserved
This read-only field is reserved and always has the value zero.
21–16
PCS[5:0]
Select which PCS signals are to be asserted for the transfer. Refer to the chip configuration chapter for
the number of PCS signals used in this MCU.
0 Negate the PCS[x] signal.
1 Assert the PCS[x] signal.
15–0
TXDATA
Transmit Data
Holds SPI data to be transferred according to the associated SPI command.
46.3.8 DSPI PUSH TX FIFO Register In Slave Mode
(SPIx_PUSHR_SLAVE)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the PUSHR transfer all
32 register bits to the TX FIFO. The register structure is different in master and slave
modes. In master mode the register provides 16-bit command and 16-bit data to the TX
FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
frame operation.
Addresses: SPI0_PUSHR_SLAVE is 4002_C000h base + 34h offset = 4002_C034h
SPI1_PUSHR_SLAVE is 4002_D000h base + 34h offset = 4002_D034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1227