Information

46.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)
TXFRn provide visibility into the TX FIFO for debugging purposes. Each register is an
entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the
TXFRx registers does not alter the state of the TX FIFO.
Addresses: SPI0_TXFR0 is 4002_C000h base + 3Ch offset = 4002_C03Ch
SPI0_TXFR1 is 4002_C000h base + 40h offset = 4002_C040h
SPI0_TXFR2 is 4002_C000h base + 44h offset = 4002_C044h
SPI0_TXFR3 is 4002_C000h base + 48h offset = 4002_C048h
SPI1_TXFR0 is 4002_D000h base + 3Ch offset = 4002_D03Ch
SPI1_TXFR1 is 4002_D000h base + 40h offset = 4002_D040h
SPI1_TXFR2 is 4002_D000h base + 44h offset = 4002_D044h
SPI1_TXFR3 is 4002_D000h base + 48h offset = 4002_D048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXCMD_TXDATA TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_TXFRn field descriptions
Field Description
31–16
TXCMD_
TXDATA
Transmit Command or Transmit Data
In master mode the TXCMD field contains the command that sets the transfer attributes for the SPI data.
In slave mode, the TXDATA contains 16 MSB bits of the SPI data to be shifted out.
15–0
TXDATA
Transmit Data
Contains the SPI data to be shifted out.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1229