Information

If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TX

FIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. See

Transmit FIFO Underflow Interrupt Request for details.

46.4.2.5 Receive First In First Out (RX FIFO) Buffering Mechanism

The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds

4 received SPI data frames. The number of entries in the RX FIFO is device-specific. SPI

data is added to the RX FIFO at the completion of a transfer when the received data in the

shift register is transferred into the RX FIFO. SPI data are removed (popped) from the

RX FIFO by reading the DSPI POP RX FIFO Register (POPR). RX FIFO entries can

only be removed from the RX FIFO by reading the POPR or by flushing the RX FIFO.

The RX FIFO Counter field (RXCTR) in the DSPI Status Register (SR) indicates the

number of valid entries in the RX FIFO. The RXCTR is updated every time the POPR is

read or SPI data is copied from the shift register to the RX FIFO.

The POPNXTPTR field in the SR points to the RX FIFO entry that is returned when the

POPR is read. The POPNXTPTR contains the positive offset from RXFR0 in number of

32-bit registers. For example, POPNXTPTR equal to two means that the RXFR2 contains

the received SPI data that will be returned when POPR is read. The POPNXTPTR field is

incremented every time the POPR is read. The maximum value of the field is equal to the

maximum implemented RXFR register number and it rolls over after reaching the

maximum.

46.4.2.5.1 Filling the RX FIFO

The RX FIFO is filled with the received SPI data from the shift register. While the RX

FIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Every

time a SPI frame is transferred to the RX FIFO the RX FIFO Counter is incremented by

one.

If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the

SR is set indicating an overflow condition. Depending on the state of the ROOE bit in the

MCR, the data from the transfer that generated the overflow is either ignored or shifted in

to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift

Chapter 46 SPI (DSPI)

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 1235