Information

46.4.2.5.2 Draining the RX FIFO
Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the DSPI
POP RX FIFO Register (POPR). A read of the POPR decrements the RX FIFO Counter
by one. Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO
Counter remains unchanged. The data, read from the empty RX FIFO, is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the SR is set. The
RFDF bit is cleared when the RX_FIFO is empty and the DMA controller indicates that a
read from POPR is complete or by writing a '1' to it.
46.4.3 DSPI Baud Rate and Clock Delay Generation
The SCK frequency and the delay values for serial transfer are generated by dividing the
system clock frequency by a prescaler and a scaler with the option for doubling the baud
rate. The following figure shows conceptually how the SCK signal is generated.
System Clock
Prescaler
1
Scaler
1+DBR
SCK
Figure 46-70. Communications Clock Prescalers and Scalers
46.4.3.1 Baud Rate Generator
The Baud Rate is the frequency of the Serial Communication Clock (SCK). The system
clock is divided by a prescaler (PBR) and scaler (BR) to produce SCK with the
possibility of halving the scaler division. The DBR, PBR and BR fields in the CTAR
registers select the frequency of SCK by the formula in the BR field description. The
following table shows an example of how to compute the baud rate.
Table 46-80. Baud Rate Computation Example
f
sys
PBR Prescaler BR Scaler DBR Baud Rate
100 MHz 0b00 2 0b0000 2 0 25 Mb/s
20 MHz 0b00 2 0b0000 2 1 10 Mb/s
NOTE
The clock frequencies mentioned in the preceding table are
given as an example. Refer to the clocking chapter for the
frequency used to drive this module in the device.
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1236 Freescale Semiconductor, Inc.