Information

46.4.3.2 PCS to SCK Delay (t
CSC
)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first
SCK edge. See Figure 46-72 for an illustration of the PCS to SCK delay. The PCSSCK
and CSSCK fields in the CTARx registers select the PCS to SCK delay by the formula in
the CSSCK field description. The following table shows an example of how to compute
the PCS to SCK delay.
Table 46-81. PCS to SCK Delay Computation Example
f
sys
PCSSCK Prescaler CSSCK Scaler PCS to SCK Delay
100 MHz 0b01 3 0b0100 32 0.96 μs
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
46.4.3.3 After SCK Delay (t
ASC
)
The After SCK Delay is the length of time between the last edge of SCK and the negation
of PCS. See Figure 46-72 and Figure 46-73 for illustrations of the After SCK delay. The
PASC and ASC fields in the CTARx registers select the After SCK Delay by the formula
in the ASC field description. The following table shows an example of how to compute
the After SCK delay.
Table 46-82. After SCK Delay Computation Example
f
sys
PASC Prescaler ASC Scaler After SCK Delay
100 MHz 0b01 3 0b0100 32 0.96 μs
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1237