Information

46.4.3.4 Delay after Transfer (t
DT
)
The Delay after Transfer is the minimum time between negation of the PCS signal for a
frame and the assertion of the PCS signal for the next frame. See Figure 46-72 for an
illustration of the Delay after Transfer. The PDT and DT fields in the CTARx registers
select the Delay after Transfer by the formula in the DT field description. The following
table shows an example of how to compute the Delay after Transfer.
Table 46-83. Delay after Transfer Computation Example
f
sys
PDT Prescaler DT Scaler Delay after Transfer
100 MHz 0b01 3 0b1110 32768 0.98 ms
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
When in non-continuous clock mode the t
DT
delay is configured according to the
equation specified in the CTAR[DT] bitfield description. When in continuous clock
mode, the delay is fixed at 1 SCK period.
46.4.3.5 Peripheral Chip Select Strobe Enable (PCSS )
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs thereby avoiding glitches. When the DSPI is in master mode and the PCSSE bit is
set in the MCR, PCSS provides a signal for an external demultiplexer to decode the
PCS[0] - PCS[4] signals into as many as 128 glitch-free PCS signals. The following
figure shows the timing of the PCSS signal relative to PCS signals.
t
PCSSCK
PCSS
PCSx
t
PASC
Figure 46-71. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1238 Freescale Semiconductor, Inc.