Information

At the end of the transfer the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
The following table shows an example of how to compute the t
pcssck
delay.
Table 46-84. Peripheral Chip Select Strobe Assert Computation Example
f
sys
PCSSCK Prescaler Delay before Transfer
100 MHz 0b11 7 70.0 ns
The following table shows an example of how to compute the t
pasc
delay.
Table 46-85. Peripheral Chip Select Strobe Negate Computation Example
f
sys
PASC Prescaler Delay after Transfer
100 MHz 0b11 7 70.0 ns
The PCSS signal is not supported when Continuous Serial Communication SCK mode
are enabled.
NOTE
The clock frequency mentioned in the preceding tables is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
46.4.4 Transfer Formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK)
signal and the PCS signals. The SCK signal provided by the master device synchronizes
shifting and sampling of the data on the SIN and SOUT pins. The PCS signals serve as
enable signals for the slave devices.
In master mode, the CPOL and CPHA bits in the Clock and Transfer Attributes Registers
(CTARn) select the polarity and phase of the serial clock, SCK.
• CPOL - Selects the idle state polarity of the SCK
• CPHA - Selects if the data on SOUT is valid before or on the first SCK edge
Even though the bus slave does not control the SCK signal, in slave mode these values
must be identical to the master device settings to ensure proper transmission. In SPI slave
mode, only CTAR0 is used.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1239