Information

t
ASC
=
A
fter SCK delay
t
CSC =
P
CS to SCK delay
MSB first (LSBFE = 0): MSB
tDT = Delay after Transfer (minimum CS negation time)
t
CSC
Bit 1
MSB
tDT
t
ASC
PCSx/SS
Slave SOUT
Master SIN/
Master SOUT/
Slave SIN
Master and Slave
Sample
SCK
(CPOL
= 0)
1
2
3 4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
(CPOL
= 1)
Bit 6
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
LSB
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB first (LSBFE = 1): LSB
Figure 46-73. DSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8)
The master initiates the transfer by asserting the PCS signal to the slave. After the t
CSC
delay has elapsed, the master generates the first SCK edge and at the same time places
valid data on the master SOUT pin . The slave responds to the first SCK edge by placing
its first data bit on its slave SOUT pin.
At the second edge of the SCK the master and slave sample their SIN pins. For the rest of
the frame the master and the slave change the data on their SOUT pins on the odd-
numbered clock edges and sample their SIN pins on the even-numbered clock edges.
After the last clock edge occurs a delay of t
ASC
is inserted before the master negates the
PCS signal. A delay of t
DT
is inserted before a new frame transfer can be initiated by the
master.
46.4.4.3 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must
remain selected between several sequential serial transfers. The Continuous Selection
Format provides the flexibility to handle the following case. The Continuous Selection
Format is enabled for the SPI Configuration by setting the CONT bit in the SPI
command. The behavior of the PCS signals in the configurations is identical so only SPI
Configuration will be described.
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1242 Freescale Semiconductor, Inc.