Information

• When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each
SPI frame transfer, the CTAR specified by the CTAS for the frame is used.
• In all configurations, the currently selected CTAR remains in use until the start of a
frame with a different CTAR specified, or the Continuous SCK mode is terminated.
It is recommended to keep the baud rate the same while using the Continuous SCK.
Switching clock polarity between frames while using Continuous SCK can cause errors
in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into the
External Stop mode or Module Disable mode.
Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer
(t
DT
) is fixed to one SCK cycle. The following figure is the timing diagram for
Continuous SCK format with Continuous Selection disabled.
NOTE
When in Continuous SCK mode, for the SPI transfer CTAR0
should always be used, and the TXFIFO must be cleared using
the MCR[CLR_TXF] field before initiating transfer.
PCS
Master SIN
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
DT
Figure 46-76. Continuous SCK Timing Diagram (CONT=0)
If the CONT bit in the TX FIFO entry is set, PCS remains asserted between the transfers.
Under certain conditions, SCK can continue with PCS asserted, but with no data being
shifted out of SOUT (SOUT pulled high). This can cause the slave to receive incorrect
data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1245