Information

• Continuous SCK with CONT bit set and entering STOPPED state (refer to Start and
Stop of DSPI Transfers).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable
mode.
The following figure shows timing diagram for Continuous SCK format with Continuous
Selection enabled.
PCS
Master SIN
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
transfer 1 transfer 2
Figure 46-77. Continuous SCK Timing Diagram (CONT=1)
46.4.6 Slave Mode Operation Constraints
Slave mode logic shift register is buffered. This allows data streaming operation, when
the DSPI is permanently selected and data is shifted in with a constant rate.
The transmit data is transferred at second SCK clock edge of the each frame to the shift
register if the SS signal is asserted and any time when transmit data is ready and SS
signal is negated.
Received data is transferred to the receive buffer at last SCK edge of each frame, defined
by frame size programmed to the CTAR0/1 register. Then the data from the buffer is
transferred to the RXFIFO or DDR register.
If the
SS negates before that last SCK edge, the data from shift register is lost.
This buffering scheme allows to operate slave clock with higher frequency than the
system frequency. The clocks relationship is defined by the following equation.
FrameSize is the value of the CTAR0/1[FMSZ] field plus one.
3
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1246 Freescale Semiconductor, Inc.