Information

46.4.7 Interrupts/DMA Requests
The DSPI has several conditions that can only generate interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Table 46-86. Interrupt and DMA Request Conditions
Condition Flag Interrupt DMA
End of Queue (EOQ) EOQF Yes
TX FIFO Fill TFFF Yes Yes
Transfer Complete TCF Yes
TX FIFO Underflow TFUF Yes
RX FIFO Drain RFDF Yes Yes
RX FIFO Overflow RFOF Yes
Each condition has a flag bit in the DSPI Status Register (SR) and an Request Enable bit
in the DSPI DMA/Interrupt Request Select and Enable Register (RSER). The TX FIFO
Fill Flag (TFFF) and RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA
requests depending on the TFFF_DIRS and RFDF_DIRS bits in the RSER.
The DSPI module also provides a global interrupt request line, which is asserted when
any of individual interrupt requests lines is asserted.
46.4.7.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End
of Queue Request is generated when the EOQ bit in the executing SPI command is set
and the EOQF_RE bit in the RSER is set.
NOTE
This interrupt request is generated when the last bit of the SPI
frame with EOQ bit set is transmitted.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1247